All Stories

  1. CollectiveHLS: A Collaborative Approach to High-Level Synthesis Design Optimization
  2. Data-driven HLS optimization for reconfigurable accelerators
  3. Late Breaking Results: Language-level QoR modeling for High-Level Synthesis
  4. Seamless HW-accelerated AI serving in heterogeneous MEC Systems with AI@EDGE
  5. Beyond RSS: Towards Intelligent Dynamic Memory Management (Work in Progress)
  6. A Framework for the Protection of Critical Infrastructures from Combined Cyber and Physical Threats
  7. The Unexpected Efficiency of Bin Packing Algorithms for Dynamic Storage Allocation in the Wild: An Intellectual Abstract
  8. A Methodology for enhancing Emergency Situational Awareness through Social Media
  9. Hardware Approximate Techniques for Deep Neural Network Accelerators: A Survey
  10. FADE
  11. Process Variability Analysis in Interconnect, Logic, and Arithmetic Blocks of 16-nm FinFET FPGAs
  12. Improving Power of DSP and CNN Hardware Accelerators Using Approximate Floating-point Multipliers
  13. FPGA Acceleration of Short Read Alignment
  14. Improving Performance-Power-Programmability in Space Avionics with Edge Devices: VBN on Myriad2 SoC
  15. EVOLVE
  16. Scale-out beam longitudinal dynamics simulations
  17. A Closed-Loop Controller to Ensure Performance and Temperature Constraints for Dynamic Applications
  18. Cooperative Arithmetic-Aware Approximation Techniques for Energy-Efficient Multipliers
  19. Oops
  20. Energy-Efficient VLSI Implementation of Multipliers with Double LSB Operands
  21. Single- and Multi-FPGA Acceleration of Dense Stereo Vision for Planetary Rovers
  22. PVT-Aware Sensing and Voltage Scaling for Energy Efficient FPGAs
  23. OpenCL-based Virtual Prototyping and Simulation of Many-Accelerator Architectures
  24. Distributed Trade-Based Edge Device Management in Multi-Gateway IoT
  25. A Hierarchical Distributed Runtime Resource Management Scheme for NoC-Based Many-Cores
  26. A Framework Exploiting Process Variability to Improve Energy Efficiency in FPGA Applications
  27. High-Performance Embedded Computing in Space: Evaluation of Platforms for Vision-Based Navigation
  28. Runtime Slack Creation for Processor Performance Variability using System Scenarios
  29. SoftRM
  30. BrainFrame: A node-level heterogeneous accelerator platform for neuron simulations
  31. AEGLE's Cloud Infrastructure for Resource Monitoring and Containerized Accelerated Analytics
  32. Project HIPNOS: Case Study of High Performance Avionics for Active Debris Removal in Space
  33. Energy Efficient Adaptive Approach for Dependable Performance in the presence of Timing Interference
  34. FabSpace 2.0: A platform for application and service development based on Earth Observation data
  35. Spark acceleration on FPGAs: A use case on machine learning in Pynq
  36. An Exploration Framework for Efficient High-Level Synthesis of Support Vector Machines: Case Study on ECG Arrhythmia Detection for Xilinx Zynq SoC
  37. Application performance improvement by exploiting process variability on FPGA devices
  38. A low-complexity control mechanism targeting smart thermostats
  39. HARPA: Tackling physically induced performance variability
  40. A Framework for Interconnection-Aware Domain-Specific Many-Accelerator Synthesis
  41. Parameter Sensitivity in Virtual FPGA Architectures
  42. CF-TUNE: Collaborative Filtering Auto-Tuning for Energy Efficient Many-core Processors
  43. Dataflow Acceleration of scikit-learn Gaussian Process Regression
  44. Optimizing Extended Hodgkin-Huxley Neuron Model Simulations for a Xeon/Xeon Phi Node
  45. Agora: Agent and market-based resource management for many-core systems
  46. Computation offloading and resource allocation for low-power IoT edge devices
  47. A 56 Gbaud reconfigurable FPGA feed-forward equalizer for optical datacenter networks with flexible baudrate- and modulation-format
  48. A Flexible, High-Performance FPGA Implementation of a Feed-Forward Equalizer for Optical Interconnects up to 112 Gb/s
  49. A Customizable Framework for Application Implementation onto 3-D FPGAs
  50. Design-Efficient Approximate Multiplication Circuits Through Partial Product Perforation
  51. Improving Dynamic Memory Allocation on Many-Core Embedded Systems With Distributed Shared Memory
  52. A survey on reconfigurable accelerators for cloud computing
  53. HW/SW Codesign and FPGA Acceleration of Visual Odometry Algorithms for Rover Navigation on Mars
  54. An Integrated Exploration and Virtual Platform Framework for Many-Accelerator Heterogeneous Systems
  55. A Systematic Methodology for Optimization of Applications Utilizing Concurrent Data Structures
  56. A framework for exploring alternative fault-tolerant schemes targeting 3-D reconfigurable architectures
  57. Performance and energy evaluation of spark applications on low-power SoCs
  58. An OpenCL-based framework for rapid virtual prototyping of heterogeneous architectures
  59. Performance-power exploration of software-defined big data analytics: The AEGLE cloud backend
  60. Near-Static Shading Exploration for Smart Photovoltaic Module Topologies Based on Snake-like Configurations
  61. Accuracy of Quasi-Monte Carlo technique in failure probability estimations
  62. ANT3D: Simultaneous Partitioning and Placement for 3-D FPGAs based on Ant Colony Optimization
  63. First impressions from detailed brain model simulations on a Xeon/Xeon-Phi node
  64. Parallel application placement onto 3-D reconfigurable architectures
  65. ECG signal analysis and arrhythmia detection on IoT wearable medical devices
  66. Customization methodology for implementation of streaming aggregation in embedded systems
  67. Performance analysis of accelerated biophysically-meaningful neuron simulations
  68. Efficient variability analysis of arithmetic units using linear regression techniques
  69. Runtime Interval Optimization and Dependable Performance for Application-Level Checkpointing
  70. Runtime management of adaptive MPSoCs for graceful degradation
  71. Capturing True Workload Dependency of BTI-induced Degradation in CPU Components
  72. A Survey on FEC Codes for 100 G and Beyond Optical Networks
  73. A Co-Design Approach For Rapid Prototyping Of Image Processing On SoC FPGAs
  74. The VINEYARD Approach: Versatile, Integrated, Accelerator-Based, Heterogeneous Data Centres
  75. Deploying and monitoring hadoop MapReduce analytics on single-chip cloud computer
  76. Distributed QoS management for internet of things under resource constraints
  77. An Evolutionary Algorithm for Netlist Partitioning Targeting 3-D FPGAs
  78. A MapReduce scratchpad memory for multi-core cloud computing applications
  79. Advancing Integrated and Personalized Healthcare Services, the AEGLE Approach
  80. Job-Arrival Aware Distributed Run-Time Resource Management on Intel SCC Manycore Platform
  81. Rapid prototyping and Design Space Exploration methodologies for many-accelerator systems
  82. High-Level-Synthesis extensions for scalable Single-Chip Many-Accelerators on FPGAs
  83. Preface
  84. Tackling Performance Variability Due to RAS Mechanisms with PID-Controlled DVFS
  85. Platform-aware dynamic data type refinement methodology for radix tree Data Structures
  86. Many-core CPUs can deliver scalable performance to stochastic simulations of large-scale biochemical reaction networks
  87. Hybrid approximate multiplier architectures for improved power-accuracy trade-offs
  88. Mitigating Memory-Induced Dark Silicon in Many-Accelerator Architectures
  89. HARPA: Solutions for dependable performance under physically induced performance variability
  90. AEGLE: A big bio-data analytics framework for integrated health-care services
  91. Efficient Reliability Analysis of Processor Datapath using Atomistic BTI Variability Models
  92. Classification Framework for Analysis and Modeling of Physically Induced Reliability Violations
  93. Demonstrating HW–SW Transient Error Mitigation on the Single-Chip Cloud Computer Data Plane
  94. Placement of Linked Dynamic Data Structures over Heterogeneous Memories in Embedded Systems
  95. GENESIS
  96. SPARTAN/SEXTANT/COMPASS: Advancing Space Rover Vision via Reconfigurable Platforms
  97. Trusted Computing for Embedded Systems
  98. Applied Reconfigurable Computing
  99. Dynamic Memory Management for Embedded Systems
  100. Reconfigurable Computing for Analytics Acceleration of Big Bio-Data: The AEGLE Approach
  101. Using Chaos Theory based workload analysis to perform Dynamic Frequency Scaling on MPSoCs
  102. An Energy Efficient Message Passing Synchronization Algorithm for Concurrent Data Structures in Embedded Systems
  103. SWAN-iCARE Project: On the Efficiency of FPGAs Emulating Wearable Medical Devices for Wound Management and Monitoring
  104. A Novel Concept for Adaptive Signal Processing on Reconfigurable Hardware
  105. TEAChER: TEach AdvanCEd Reconfigurable Architectures and Tools
  106. Effective Learning and Filtering of Faulty Heart-Beats for Advanced ECG Arrhythmia Detection using MIT-BIH Database
  107. Plug&Chip
  108. A Framework for Supporting Adaptive Fault-Tolerant Solutions
  109. Linear regression techniques for efficient analysis of transistor variability
  110. A MapReduce framework implementation for Network-on-Chip platforms
  111. Heap Management for Trusted Operating Environments
  112. Reconfigurable FEC codes for software-defined optical transceivers
  113. A Reconfigurable MapReduce accelerator for multi-core all-programmable SoCs
  114. Introduction
  115. Intermediate Variable Removal from Dynamic Applications
  116. Systematic Placement of Dynamic Objects Across Heterogeneous Memory Hierarchies
  117. Dynamic Data Types Optimization in Multimedia and Communication Applications
  118. Analysis and Characterization of Dynamic Multimedia Applications
  119. Profiling and Analysis of Dynamic Applications
  120. Dynamic Memory Management Optimization for Multimedia Applications
  121. Systematic Exploration of Power-Aware Scenarios for IEEE 802.11ac WLAN Systems
  122. Performance and power consumption evaluation of concurrent queue implementations in embedded systems
  123. Evaluation of message passing synchronization algorithms in embedded systems
  124. Optimal mapping of inferior olive neuron simulations on the Single-Chip Cloud Computer
  125. A framework for rapid evaluation of heterogeneous 3-D NoC architectures
  126. Understanding timing impact of BTI/RTN with massively threaded atomistic transient simulations
  127. A Framework for Mapping Dynamic Virtual Kernels onto Heterogeneous Reconfigurable Platforms
  128. A Framework for Customizing Virtual 3-D Reconfigurable Platforms at Run-Time
  129. A Low-Latency Algorithm and FPGA Design for the Min-Search of LDPC Decoders
  130. The Enexal Bauxite Residue Treatment Process: Industrial Scale Pilot Plant Results
  131. Designing 2D and 3D Network-on-Chip Architectures
  132. A novel 3-D FPGA architecture targeting communication intensive applications
  133. Hardware Accelerated Rician Denoise Algorithm for High Performance Magnetic Resonance Imaging
  134. A HW/SW Framework Emulating Wearable Devices For Remote Wound Monitoring and Management
  135. Effective Platform-Level Exploration for Heterogeneous Multicores Exploiting Simulation-Induced Slacks
  136. Power-aware dynamic memory management on many-core platforms utilizing DVFS
  137. A low-cost fault tolerant solution targeting commercial FPGA devices
  138. SPARTAN: Developing a Vision System for Future Autonomous Space Exploration Robots
  139. The SYSMANTIC NoC Design and Prototyping Framework
  140. NoC-Based System Integration
  141. Projects on Network-on-Chip
  142. NoC Verification and Testing
  143. Communication Architecture
  144. Middleware Memory Management in NoC
  145. Power and Thermal Effects and Management
  146. NoC Modeling and Topology Exploration
  147. The Spidergon STNoC
  148. On Designing 3-D Platforms
  149. Network-on-Chip Technology: A Paradigm Shift
  150. A platform-independent runtime methodology for mapping multiple applications onto FPGAs through resource virtualization
  151. A low-complexity implementation of QC-LDPC encoder in reconfigurable logic
  152. Automatic implementation of low-complexity QC-LDPC encoders
  153. Automatic implementation of low-complexity QC-LDPC encoders
  154. System scenarios-based architecture level exploration of SDR application using a network-on-chip simulation framework
  155. A Process-based Reconfigurable SystemC Module for simulation speedup
  156. JITPR
  157. SWAN-iCare: A smart wearable and autonomous negative pressure device for wound monitoring and therapy
  158. Arterial Dissection
  159. On Supporting Adaptive Fault Tolerant at Run-Time with Virtual FPGAs
  160. HVSoCs: A Framework for Rapid Prototyping of 3-D Hybrid Virtual System-on-Chips
  161. Hypervised Transient SPICE Simulations of Large Netlists & Workloads on Multi-Processor Systems
  162. Performance Evaluation of Embedded Processor in MapReduce Cloud Computing Applications
  163. Distributed run-time resource management for malleable applications on many-core platforms
  164. Run-Time Measurement of Harvested Energy for Autarkic Sensor Operation
  165. Compiler-in-the-loop exploration during datapath synthesis for higher quality delay-area trade-offs
  166. High-level customization framework for application-specific NoC architectures
  167. Enabling Efficient System Configurations for Dynamic Wireless Applications Using System Scenarios
  168. Adaptive dynamic memory allocators by estimating application workloads
  169. Systematic design and evaluation of a scalable reconfigurable multiplier scheme for HLS environments
  170. A low-cost fault tolerant solution targeting to commercial FPGA devices
  171. On Supporting Efficient Partial Reconfiguration with Just-In-Time Compilation
  172. A novel framework for exploring 3-D FPGAs with heterogeneous interconnect fabric
  173. Scalable Multi-core Architectures
  174. A Systematic Methodology for Reliability Improvements on SoC-Based Software Defined Radio Systems
  175. Framework for performing rapid evaluation of 3D SoCs
  176. Design and experimentation with low-power morphable multipliers
  177. Power, performance and area prediction of 3D ICs during early stage design exploration in 45nm
  178. Low-Power Reconfigurable Component Utilization in a High-Level Synthesis Flow
  179. Enabling efficient system configurations for dynamic wireless baseband engines using system scenarios
  180. Application-Specific Multi-Threaded Dynamic Memory Management
  181. A Framework for Architecture-Level Exploration of Communication Intensive Applications onto 3-D FPGAs
  182. A Methodology and Tool Framework for Supporting Rapid Exploration of Memory Hierarchies in FPGAs
  183. Thermal optimization for micro-architectures through selective block replication
  184. Custom Microcoded Dynamic Memory Management for Distributed On-Chip Memory Organizations
  185. FILESPPA: Fast Instruction Level Embedded System Power and Performance Analyzer
  186. CAD tools for designing 3D integrated systems
  187. Keynote speech 2: Reconfigurable systems and 3D architectures
  188. A reconfigurable IP characterization technique improving high-level synthesis results
  189. A novel methodology for architecture-level exploration of 3D SoCs
  190. A standard-cell library suite for deep-deep sub-micron CMOS technologies
  191. High Performance and Area Efficient Flexible DSP Datapath Synthesis
  192. On Supporting Rapid Thermal Analysis
  193. Three Dimensional System Integration
  194. A High Level Synthesis Exploration Framework with Iterative Design Space Partitioning
  195. Mapping Embedded Applications on MPSoCs: The MNEMEE Approach
  196. The MOSART Mapping Optimization for Multi-Core ARchiTectures
  197. A Framework for Architecture-Level Exploration of 3-D FPGA Platforms
  198. A Temperature-Aware Time-Dependent Dielectric Breakdown Analysis Framework
  199. Multiple Vdd on 3D NoC architectures
  200. A Methodology for Alleviating the Performance Degradation of TMR Solutions
  201. BIT-width exploration over 3D architectures using high-level synthesis
  202. Introduction to Three-Dimensional Integration
  203. Towards Supporting Fault-Tolerance in FPGAs
  204. A High-Level Mapping Algorithm Targeting 3D NoC Architectures with Multiple Vdd
  205. High-Level Synthesis Methodologies for Delay-Area Optimized Coarse-Grained Reconfigurable Coprocessor Architectures
  206. Systematic Exploration of Energy-Efficient Application-Specific Network-on-Chip Architectures
  207. Efficient High Level Synthesis Exploration Methodology Combining Exhaustive and Gradient-Based Pruned Searching
  208. Custom multi-threaded Dynamic Memory Management for Multiprocessor System-on-Chip platforms
  209. Mapping Optimisation for Scalable Multi-core ARchiTecture: The MOSART Approach
  210. Mapping Embedded Applications on MPSoCs: The MNEMEE Approach
  211. Software metadata: Systematic characterization of the memory behaviour of dynamic applications
  212. Designing efficient DSP datapaths through compiler-in-the-loop exploration methodology
  213. A NOVEL ALLOCATION METHODOLOGY FOR PARTIAL AND DYNAMIC BITSTREAM GENERATION FOR FPGA ARCHITECTURES
  214. Construction of dual mode components for reconfiguration aware high-level synthesis
  215. VLSI-SoC: Design Methodologies for SoC and SiP
  216. Fast Instruction Memory Hierarchy Power Exploration for Embedded Systems
  217. A framework for automatic parallelization, static and dynamic memory optimization in MPSoC platforms
  218. A Temperature-Aware Placement and Routing Algorithm Targeting 3D FPGAs
  219. A Framework for Enabling Fault Tolerance in Reconfigurable Architectures
  220. Multi-granularity NoC Simulation Framework for Early Phase Exploration of SDR Hardware Platforms
  221. MNEMEE
  222. Dynamic Data Type Optimization and Memory Assignment Methodologies
  223. Application-Specific Temperature Reduction Systematic Methodology for 2D and 3D Networks-on-Chip
  224. Compilation Technique for Loop Overhead Minimization
  225. Three dimensional FPGA architectures: A shift paradigm for energy-performance efficient DSP implementations
  226. Node resource management for DSP applications on 3D Network-on-Chip architecture
  227. Optimization methodology of dynamic data structures based on genetic algorithms for multimedia embedded systems
  228. A software-supported methodology for exploring interconnection architectures targeting 3-D FPGAs
  229. Three-Dimensional Networks-on-Chip Architectures
  230. An Efficient Approach for Managing Power Consumption Hotspots Distribution on 3D FPGAs
  231. A Power-Aware Placement and Routing Algorithm Targeting 3D FPGAs
  232. Aortic Function in Beta-Thalassemia Major
  233. Exploration methodology of dynamic data structures in multimedia and network applications for embedded platforms
  234. Designing a novel high-performance FPGA architecture for data intensive applications
  235. Mapping DSP Applications onto High-Performance Architectural Templates with Inlined Flexibility
  236. Designing a General-Purpose Interconnection Architecture for Field Programmable Gate Arrays
  237. Enabling run-time memory data transfer optimizations at the system level with automated extraction of embedded software metadata information
  238. Architecture-Level Exploration of Alternative Interconnection Schemes Targeting 3D FPGAs: A Software-Supported Methodology
  239. A software-supported methodology for designing high-performance 3D FPGA architectures
  240. Implementing cellular automata modeled applications on network-on-chip platforms
  241. Systematic methodology for exploration of performance – Energy trade-offs in network applications using Dynamic Data Type refinement
  242. Middleware Design Optimization of Wireless Protocols Based on the Exploitation of Dynamic Input Patterns
  243. Preface of Special Issue on VLSI Design and Test
  244. Preface
  245. Fine- and Coarse-Grain Reconfigurable Computing
  246. A Novel Methodology for Temperature-Aware Placement and Routing of FPGAs
  247. Optimization of dynamic data structures in multimedia embedded systems using evolutionary computation
  248. Application - specific NoC platform design based on System Level Optimization
  249. Efficient Power Management Strategy of FPGAs Using a Novel Placement Technique
  250. An Estimation Methodology for Designing Instruction Cache Memory of Embedded Systems
  251. Reducing memory fragmentation in network applications with dynamic memory allocators optimized for performance
  252. Behavioral-Level Performance and Power Exploration of Data-Intensive Applications Mapped on Programmable Processors
  253. Systematic dynamic memory management design methodology for reduced memory footprint
  254. Efficient system-level prototyping of power-aware dynamic memory managers for embedded systems
  255. Wire Segment Length and Switch Box Co-Optimization for FPGA Architectures
  256. Energy-efficient dynamic memory allocators at the middleware level of embedded systems
  257. A novel methodology for designing high-performance and low-energy FPGA routing architecture
  258. Designing Alternative FPGA Implementations Using Spatial Data from Hardware Resources
  259. Circuits Techniques for Dynamic Power Reduction
  260. A method for partitioning applications in hybrid reconfigurable architectures
  261. Editorial: Power and timing modelling, optimisation and simulation
  262. Reducing Memory Fragmentation with Performance-Optimized Dynamic Memory Allocators in Network Applications
  263. Improving the Memory Bandwidth Utilization Using Loop Transformations
  264. International EMS systems: Greece
  265. Circuits Techniques for Dynamic Power Reduction
  266. A Novel Data-Path for Accelerating DSP Kernels
  267. Design of Energy Efficient Wireless Networks Using Dynamic Data Type Refinement Methodology
  268. Power, Performance and Area Exploration for Data Memory Assignment of Multimedia Applications
  269. Designing CMOS Circuits for Low Power
  270. Motivation, Context and Objectives
  271. Logic Level Power Optimization
  272. Sources of Power Dissipation in CMOS Circuits
  273. THE DESIGN OF A RIPPLE CARRY ADIABATIC ADDER
  274. Integrated Circuit Design
  275. Run-Time Power Management for Low and Medium Bit-Rate Digital Receivers
  276. Mapping iterative algorithims on regular processor arrays without using uniform recurrent equations
  277. Ateleological Developments of "Design-Decisions-Independent" Information Systems
  278. Designing Heterogeneous FPGAs with Multiple SBs
  279. System-Level Application-Specific NoC Design for Network and Multimedia Applications
  280. Direct Memory Access Optimization in Wireless Terminals for Reduced Memory Latency and Energy Consumption
  281. Systematic design of novel architectures for implementation of Radon Transform
  282. Designing efficient redundant arithmetic processors for DSP applications
  283. Design methodology for direct mapping of iterative algorithms on array architectures
  284. Design methodology of mapping iterative algorithms on piecewise regular processor arrays
  285. Methodology for the design of signed-digit DSP processors
  286. A Partitioning Methodology for Accelerating Applications in Hybrid Reconfigurable Platforms
  287. A window-based color quantization technique and its embedded implementation
  288. A novel division algorithm for parallel and sequential processing
  289. Methodology for the design of signed-digit DSP processors
  290. A systematic methodology for designing multilevel systolic architectures
  291. Abstract and Concrete Data Type Optimizations at the UML and C/C++ Level for Dynamic Embedded Software
  292. Data and instruction memory performance and energy optimization technique
  293. A Survey of Coarse-Grain Reconfigurable Architectures and Cad Tools
  294. A Survey of Existing Fine-Grain Reconfigurable Architectures and CAD tools
  295. A low-energy FPGA: architecture design and software-supported design flow
  296. A Methodology for Partitioning DSP Applications in Hybrid Reconfigurable Systems
  297. A Petri net approach to the design of processor array architectures
  298. A systematic methodology for designing multilevel systolic architectures
  299. Low-power design of array architectures