All Stories

  1. CollectiveHLS: A Collaborative Approach to High-Level Synthesis Design Optimization
  2. Seamless HW-accelerated AI serving in heterogeneous MEC Systems with AI@EDGE
  3. Beyond RSS: Towards Intelligent Dynamic Memory Management (Work in Progress)
  4. A Framework for the Protection of Critical Infrastructures from Combined Cyber and Physical Threats
  5. The Unexpected Efficiency of Bin Packing Algorithms for Dynamic Storage Allocation in the Wild: An Intellectual Abstract
  6. A Methodology for enhancing Emergency Situational Awareness through Social Media
  7. Hardware Approximate Techniques for Deep Neural Network Accelerators: A Survey
  8. FADE
  9. Process Variability Analysis in Interconnect, Logic, and Arithmetic Blocks of 16-nm FinFET FPGAs
  10. Improving Power of DSP and CNN Hardware Accelerators Using Approximate Floating-point Multipliers
  11. FPGA Acceleration of Short Read Alignment
  12. Improving Performance-Power-Programmability in Space Avionics with Edge Devices: VBN on Myriad2 SoC
  13. EVOLVE
  14. Scale-out beam longitudinal dynamics simulations
  15. A Closed-Loop Controller to Ensure Performance and Temperature Constraints for Dynamic Applications
  16. Cooperative Arithmetic-Aware Approximation Techniques for Energy-Efficient Multipliers
  17. Oops
  18. Energy-Efficient VLSI Implementation of Multipliers with Double LSB Operands
  19. Single- and Multi-FPGA Acceleration of Dense Stereo Vision for Planetary Rovers
  20. PVT-Aware Sensing and Voltage Scaling for Energy Efficient FPGAs
  21. OpenCL-based Virtual Prototyping and Simulation of Many-Accelerator Architectures
  22. Distributed Trade-Based Edge Device Management in Multi-Gateway IoT
  23. A Hierarchical Distributed Runtime Resource Management Scheme for NoC-Based Many-Cores
  24. A Framework Exploiting Process Variability to Improve Energy Efficiency in FPGA Applications
  25. High-Performance Embedded Computing in Space: Evaluation of Platforms for Vision-Based Navigation
  26. Runtime Slack Creation for Processor Performance Variability using System Scenarios
  27. SoftRM
  28. BrainFrame: A node-level heterogeneous accelerator platform for neuron simulations
  29. AEGLE's Cloud Infrastructure for Resource Monitoring and Containerized Accelerated Analytics
  30. Project HIPNOS: Case Study of High Performance Avionics for Active Debris Removal in Space
  31. Energy Efficient Adaptive Approach for Dependable Performance in the presence of Timing Interference
  32. FabSpace 2.0: A platform for application and service development based on Earth Observation data
  33. Spark acceleration on FPGAs: A use case on machine learning in Pynq
  34. An Exploration Framework for Efficient High-Level Synthesis of Support Vector Machines: Case Study on ECG Arrhythmia Detection for Xilinx Zynq SoC
  35. Application performance improvement by exploiting process variability on FPGA devices
  36. A low-complexity control mechanism targeting smart thermostats
  37. HARPA: Tackling physically induced performance variability
  38. A Framework for Interconnection-Aware Domain-Specific Many-Accelerator Synthesis
  39. Parameter Sensitivity in Virtual FPGA Architectures
  40. CF-TUNE: Collaborative Filtering Auto-Tuning for Energy Efficient Many-core Processors
  41. Dataflow Acceleration of scikit-learn Gaussian Process Regression
  42. Optimizing Extended Hodgkin-Huxley Neuron Model Simulations for a Xeon/Xeon Phi Node
  43. Agora: Agent and market-based resource management for many-core systems
  44. Computation offloading and resource allocation for low-power IoT edge devices
  45. A 56 Gbaud reconfigurable FPGA feed-forward equalizer for optical datacenter networks with flexible baudrate- and modulation-format
  46. A Flexible, High-Performance FPGA Implementation of a Feed-Forward Equalizer for Optical Interconnects up to 112 Gb/s
  47. A Customizable Framework for Application Implementation onto 3-D FPGAs
  48. Design-Efficient Approximate Multiplication Circuits Through Partial Product Perforation
  49. Improving Dynamic Memory Allocation on Many-Core Embedded Systems With Distributed Shared Memory
  50. A survey on reconfigurable accelerators for cloud computing
  51. HW/SW Codesign and FPGA Acceleration of Visual Odometry Algorithms for Rover Navigation on Mars
  52. An Integrated Exploration and Virtual Platform Framework for Many-Accelerator Heterogeneous Systems
  53. A Systematic Methodology for Optimization of Applications Utilizing Concurrent Data Structures
  54. A framework for exploring alternative fault-tolerant schemes targeting 3-D reconfigurable architectures
  55. Performance and energy evaluation of spark applications on low-power SoCs
  56. An OpenCL-based framework for rapid virtual prototyping of heterogeneous architectures
  57. Performance-power exploration of software-defined big data analytics: The AEGLE cloud backend
  58. Near-Static Shading Exploration for Smart Photovoltaic Module Topologies Based on Snake-like Configurations
  59. Accuracy of Quasi-Monte Carlo technique in failure probability estimations
  60. ANT3D: Simultaneous Partitioning and Placement for 3-D FPGAs based on Ant Colony Optimization
  61. First impressions from detailed brain model simulations on a Xeon/Xeon-Phi node
  62. Parallel application placement onto 3-D reconfigurable architectures
  63. ECG signal analysis and arrhythmia detection on IoT wearable medical devices
  64. Customization methodology for implementation of streaming aggregation in embedded systems
  65. Performance analysis of accelerated biophysically-meaningful neuron simulations
  66. Efficient variability analysis of arithmetic units using linear regression techniques
  67. Runtime Interval Optimization and Dependable Performance for Application-Level Checkpointing
  68. Runtime management of adaptive MPSoCs for graceful degradation
  69. Capturing True Workload Dependency of BTI-induced Degradation in CPU Components
  70. A Survey on FEC Codes for 100 G and Beyond Optical Networks
  71. A Co-Design Approach For Rapid Prototyping Of Image Processing On SoC FPGAs
  72. The VINEYARD Approach: Versatile, Integrated, Accelerator-Based, Heterogeneous Data Centres
  73. Deploying and monitoring hadoop MapReduce analytics on single-chip cloud computer
  74. Distributed QoS management for internet of things under resource constraints
  75. An Evolutionary Algorithm for Netlist Partitioning Targeting 3-D FPGAs
  76. A MapReduce scratchpad memory for multi-core cloud computing applications
  77. Advancing Integrated and Personalized Healthcare Services, the AEGLE Approach
  78. Job-Arrival Aware Distributed Run-Time Resource Management on Intel SCC Manycore Platform
  79. Rapid prototyping and Design Space Exploration methodologies for many-accelerator systems
  80. High-Level-Synthesis extensions for scalable Single-Chip Many-Accelerators on FPGAs
  81. Preface
  82. Tackling Performance Variability Due to RAS Mechanisms with PID-Controlled DVFS
  83. Platform-aware dynamic data type refinement methodology for radix tree Data Structures
  84. Many-core CPUs can deliver scalable performance to stochastic simulations of large-scale biochemical reaction networks
  85. Hybrid approximate multiplier architectures for improved power-accuracy trade-offs
  86. Mitigating Memory-Induced Dark Silicon in Many-Accelerator Architectures
  87. HARPA: Solutions for dependable performance under physically induced performance variability
  88. AEGLE: A big bio-data analytics framework for integrated health-care services
  89. Efficient Reliability Analysis of Processor Datapath using Atomistic BTI Variability Models
  90. Classification Framework for Analysis and Modeling of Physically Induced Reliability Violations
  91. Demonstrating HW–SW Transient Error Mitigation on the Single-Chip Cloud Computer Data Plane
  92. Placement of Linked Dynamic Data Structures over Heterogeneous Memories in Embedded Systems
  93. GENESIS
  94. SPARTAN/SEXTANT/COMPASS: Advancing Space Rover Vision via Reconfigurable Platforms
  95. Trusted Computing for Embedded Systems
  96. Applied Reconfigurable Computing
  97. Dynamic Memory Management for Embedded Systems
  98. Reconfigurable Computing for Analytics Acceleration of Big Bio-Data: The AEGLE Approach
  99. Using Chaos Theory based workload analysis to perform Dynamic Frequency Scaling on MPSoCs
  100. An Energy Efficient Message Passing Synchronization Algorithm for Concurrent Data Structures in Embedded Systems
  101. SWAN-iCARE Project: On the Efficiency of FPGAs Emulating Wearable Medical Devices for Wound Management and Monitoring
  102. A Novel Concept for Adaptive Signal Processing on Reconfigurable Hardware
  103. TEAChER: TEach AdvanCEd Reconfigurable Architectures and Tools
  104. Effective Learning and Filtering of Faulty Heart-Beats for Advanced ECG Arrhythmia Detection using MIT-BIH Database
  105. Plug&Chip
  106. A Framework for Supporting Adaptive Fault-Tolerant Solutions
  107. Linear regression techniques for efficient analysis of transistor variability
  108. A MapReduce framework implementation for Network-on-Chip platforms
  109. Heap Management for Trusted Operating Environments
  110. Reconfigurable FEC codes for software-defined optical transceivers
  111. A Reconfigurable MapReduce accelerator for multi-core all-programmable SoCs
  112. Introduction
  113. Intermediate Variable Removal from Dynamic Applications
  114. Systematic Placement of Dynamic Objects Across Heterogeneous Memory Hierarchies
  115. Dynamic Data Types Optimization in Multimedia and Communication Applications
  116. Analysis and Characterization of Dynamic Multimedia Applications
  117. Profiling and Analysis of Dynamic Applications
  118. Dynamic Memory Management Optimization for Multimedia Applications
  119. Systematic Exploration of Power-Aware Scenarios for IEEE 802.11ac WLAN Systems
  120. Performance and power consumption evaluation of concurrent queue implementations in embedded systems
  121. Evaluation of message passing synchronization algorithms in embedded systems
  122. Optimal mapping of inferior olive neuron simulations on the Single-Chip Cloud Computer
  123. A framework for rapid evaluation of heterogeneous 3-D NoC architectures
  124. Understanding timing impact of BTI/RTN with massively threaded atomistic transient simulations
  125. A Framework for Mapping Dynamic Virtual Kernels onto Heterogeneous Reconfigurable Platforms
  126. A Framework for Customizing Virtual 3-D Reconfigurable Platforms at Run-Time
  127. A Low-Latency Algorithm and FPGA Design for the Min-Search of LDPC Decoders
  128. The Enexal Bauxite Residue Treatment Process: Industrial Scale Pilot Plant Results
  129. Designing 2D and 3D Network-on-Chip Architectures
  130. A novel 3-D FPGA architecture targeting communication intensive applications
  131. Hardware Accelerated Rician Denoise Algorithm for High Performance Magnetic Resonance Imaging
  132. A HW/SW Framework Emulating Wearable Devices For Remote Wound Monitoring and Management
  133. Effective Platform-Level Exploration for Heterogeneous Multicores Exploiting Simulation-Induced Slacks
  134. Power-aware dynamic memory management on many-core platforms utilizing DVFS
  135. A low-cost fault tolerant solution targeting commercial FPGA devices
  136. SPARTAN: Developing a Vision System for Future Autonomous Space Exploration Robots
  137. The SYSMANTIC NoC Design and Prototyping Framework
  138. NoC-Based System Integration
  139. Projects on Network-on-Chip
  140. NoC Verification and Testing
  141. Communication Architecture
  142. Middleware Memory Management in NoC
  143. Power and Thermal Effects and Management
  144. NoC Modeling and Topology Exploration
  145. The Spidergon STNoC
  146. On Designing 3-D Platforms
  147. Network-on-Chip Technology: A Paradigm Shift
  148. A platform-independent runtime methodology for mapping multiple applications onto FPGAs through resource virtualization
  149. A low-complexity implementation of QC-LDPC encoder in reconfigurable logic
  150. Automatic implementation of low-complexity QC-LDPC encoders
  151. Automatic implementation of low-complexity QC-LDPC encoders
  152. System scenarios-based architecture level exploration of SDR application using a network-on-chip simulation framework
  153. A Process-based Reconfigurable SystemC Module for simulation speedup
  154. JITPR
  155. SWAN-iCare: A smart wearable and autonomous negative pressure device for wound monitoring and therapy
  156. Arterial Dissection
  157. On Supporting Adaptive Fault Tolerant at Run-Time with Virtual FPGAs
  158. HVSoCs: A Framework for Rapid Prototyping of 3-D Hybrid Virtual System-on-Chips
  159. Hypervised Transient SPICE Simulations of Large Netlists & Workloads on Multi-Processor Systems
  160. Performance Evaluation of Embedded Processor in MapReduce Cloud Computing Applications
  161. Distributed run-time resource management for malleable applications on many-core platforms
  162. Run-Time Measurement of Harvested Energy for Autarkic Sensor Operation
  163. Compiler-in-the-loop exploration during datapath synthesis for higher quality delay-area trade-offs
  164. High-level customization framework for application-specific NoC architectures
  165. Enabling Efficient System Configurations for Dynamic Wireless Applications Using System Scenarios
  166. Adaptive dynamic memory allocators by estimating application workloads
  167. Systematic design and evaluation of a scalable reconfigurable multiplier scheme for HLS environments
  168. A low-cost fault tolerant solution targeting to commercial FPGA devices
  169. On Supporting Efficient Partial Reconfiguration with Just-In-Time Compilation
  170. A novel framework for exploring 3-D FPGAs with heterogeneous interconnect fabric
  171. Scalable Multi-core Architectures
  172. A Systematic Methodology for Reliability Improvements on SoC-Based Software Defined Radio Systems
  173. Framework for performing rapid evaluation of 3D SoCs
  174. Design and experimentation with low-power morphable multipliers
  175. Power, performance and area prediction of 3D ICs during early stage design exploration in 45nm
  176. Low-Power Reconfigurable Component Utilization in a High-Level Synthesis Flow
  177. Enabling efficient system configurations for dynamic wireless baseband engines using system scenarios
  178. Application-Specific Multi-Threaded Dynamic Memory Management
  179. A Framework for Architecture-Level Exploration of Communication Intensive Applications onto 3-D FPGAs
  180. A Methodology and Tool Framework for Supporting Rapid Exploration of Memory Hierarchies in FPGAs
  181. Thermal optimization for micro-architectures through selective block replication
  182. Custom Microcoded Dynamic Memory Management for Distributed On-Chip Memory Organizations
  183. FILESPPA: Fast Instruction Level Embedded System Power and Performance Analyzer
  184. CAD tools for designing 3D integrated systems
  185. Keynote speech 2: Reconfigurable systems and 3D architectures
  186. A reconfigurable IP characterization technique improving high-level synthesis results
  187. A novel methodology for architecture-level exploration of 3D SoCs
  188. A standard-cell library suite for deep-deep sub-micron CMOS technologies
  189. High Performance and Area Efficient Flexible DSP Datapath Synthesis
  190. On Supporting Rapid Thermal Analysis
  191. Three Dimensional System Integration
  192. A High Level Synthesis Exploration Framework with Iterative Design Space Partitioning
  193. Mapping Embedded Applications on MPSoCs: The MNEMEE Approach
  194. The MOSART Mapping Optimization for Multi-Core ARchiTectures
  195. A Framework for Architecture-Level Exploration of 3-D FPGA Platforms
  196. A Temperature-Aware Time-Dependent Dielectric Breakdown Analysis Framework
  197. Multiple Vdd on 3D NoC architectures
  198. A Methodology for Alleviating the Performance Degradation of TMR Solutions
  199. BIT-width exploration over 3D architectures using high-level synthesis
  200. Introduction to Three-Dimensional Integration
  201. Towards Supporting Fault-Tolerance in FPGAs
  202. A High-Level Mapping Algorithm Targeting 3D NoC Architectures with Multiple Vdd
  203. High-Level Synthesis Methodologies for Delay-Area Optimized Coarse-Grained Reconfigurable Coprocessor Architectures
  204. Systematic Exploration of Energy-Efficient Application-Specific Network-on-Chip Architectures
  205. Efficient High Level Synthesis Exploration Methodology Combining Exhaustive and Gradient-Based Pruned Searching
  206. Custom multi-threaded Dynamic Memory Management for Multiprocessor System-on-Chip platforms
  207. Mapping Optimisation for Scalable Multi-core ARchiTecture: The MOSART Approach
  208. Mapping Embedded Applications on MPSoCs: The MNEMEE Approach
  209. Software metadata: Systematic characterization of the memory behaviour of dynamic applications
  210. Designing efficient DSP datapaths through compiler-in-the-loop exploration methodology
  211. A NOVEL ALLOCATION METHODOLOGY FOR PARTIAL AND DYNAMIC BITSTREAM GENERATION FOR FPGA ARCHITECTURES
  212. Construction of dual mode components for reconfiguration aware high-level synthesis
  213. VLSI-SoC: Design Methodologies for SoC and SiP
  214. Fast Instruction Memory Hierarchy Power Exploration for Embedded Systems
  215. A framework for automatic parallelization, static and dynamic memory optimization in MPSoC platforms
  216. A Temperature-Aware Placement and Routing Algorithm Targeting 3D FPGAs
  217. A Framework for Enabling Fault Tolerance in Reconfigurable Architectures
  218. Multi-granularity NoC Simulation Framework for Early Phase Exploration of SDR Hardware Platforms
  219. MNEMEE
  220. Dynamic Data Type Optimization and Memory Assignment Methodologies
  221. Application-Specific Temperature Reduction Systematic Methodology for 2D and 3D Networks-on-Chip
  222. Compilation Technique for Loop Overhead Minimization
  223. Three dimensional FPGA architectures: A shift paradigm for energy-performance efficient DSP implementations
  224. Node resource management for DSP applications on 3D Network-on-Chip architecture
  225. Optimization methodology of dynamic data structures based on genetic algorithms for multimedia embedded systems
  226. A software-supported methodology for exploring interconnection architectures targeting 3-D FPGAs
  227. Three-Dimensional Networks-on-Chip Architectures
  228. An Efficient Approach for Managing Power Consumption Hotspots Distribution on 3D FPGAs
  229. A Power-Aware Placement and Routing Algorithm Targeting 3D FPGAs
  230. Aortic Function in Beta-Thalassemia Major
  231. Exploration methodology of dynamic data structures in multimedia and network applications for embedded platforms
  232. Designing a novel high-performance FPGA architecture for data intensive applications
  233. Mapping DSP Applications onto High-Performance Architectural Templates with Inlined Flexibility
  234. Designing a General-Purpose Interconnection Architecture for Field Programmable Gate Arrays
  235. Enabling run-time memory data transfer optimizations at the system level with automated extraction of embedded software metadata information
  236. Architecture-Level Exploration of Alternative Interconnection Schemes Targeting 3D FPGAs: A Software-Supported Methodology
  237. A software-supported methodology for designing high-performance 3D FPGA architectures
  238. Implementing cellular automata modeled applications on network-on-chip platforms
  239. Systematic methodology for exploration of performance – Energy trade-offs in network applications using Dynamic Data Type refinement
  240. Middleware Design Optimization of Wireless Protocols Based on the Exploitation of Dynamic Input Patterns
  241. Preface of Special Issue on VLSI Design and Test
  242. Preface
  243. Fine- and Coarse-Grain Reconfigurable Computing
  244. A Novel Methodology for Temperature-Aware Placement and Routing of FPGAs
  245. Optimization of dynamic data structures in multimedia embedded systems using evolutionary computation
  246. Application - specific NoC platform design based on System Level Optimization
  247. Efficient Power Management Strategy of FPGAs Using a Novel Placement Technique
  248. An Estimation Methodology for Designing Instruction Cache Memory of Embedded Systems
  249. Reducing memory fragmentation in network applications with dynamic memory allocators optimized for performance
  250. Behavioral-Level Performance and Power Exploration of Data-Intensive Applications Mapped on Programmable Processors
  251. Systematic dynamic memory management design methodology for reduced memory footprint
  252. Efficient system-level prototyping of power-aware dynamic memory managers for embedded systems
  253. Wire Segment Length and Switch Box Co-Optimization for FPGA Architectures
  254. Energy-efficient dynamic memory allocators at the middleware level of embedded systems
  255. A novel methodology for designing high-performance and low-energy FPGA routing architecture
  256. Designing Alternative FPGA Implementations Using Spatial Data from Hardware Resources
  257. Circuits Techniques for Dynamic Power Reduction
  258. A method for partitioning applications in hybrid reconfigurable architectures
  259. Editorial: Power and timing modelling, optimisation and simulation
  260. Reducing Memory Fragmentation with Performance-Optimized Dynamic Memory Allocators in Network Applications
  261. Improving the Memory Bandwidth Utilization Using Loop Transformations
  262. International EMS systems: Greece
  263. Circuits Techniques for Dynamic Power Reduction
  264. A Novel Data-Path for Accelerating DSP Kernels
  265. Design of Energy Efficient Wireless Networks Using Dynamic Data Type Refinement Methodology
  266. Power, Performance and Area Exploration for Data Memory Assignment of Multimedia Applications
  267. Designing CMOS Circuits for Low Power
  268. Motivation, Context and Objectives
  269. Logic Level Power Optimization
  270. Sources of Power Dissipation in CMOS Circuits
  271. THE DESIGN OF A RIPPLE CARRY ADIABATIC ADDER
  272. Integrated Circuit Design
  273. Run-Time Power Management for Low and Medium Bit-Rate Digital Receivers
  274. Mapping iterative algorithims on regular processor arrays without using uniform recurrent equations
  275. Ateleological Developments of "Design-Decisions-Independent" Information Systems
  276. Designing Heterogeneous FPGAs with Multiple SBs
  277. System-Level Application-Specific NoC Design for Network and Multimedia Applications
  278. Direct Memory Access Optimization in Wireless Terminals for Reduced Memory Latency and Energy Consumption
  279. Systematic design of novel architectures for implementation of Radon Transform
  280. Designing efficient redundant arithmetic processors for DSP applications
  281. Design methodology for direct mapping of iterative algorithms on array architectures
  282. Design methodology of mapping iterative algorithms on piecewise regular processor arrays
  283. Methodology for the design of signed-digit DSP processors
  284. A Partitioning Methodology for Accelerating Applications in Hybrid Reconfigurable Platforms
  285. A window-based color quantization technique and its embedded implementation
  286. A novel division algorithm for parallel and sequential processing
  287. Methodology for the design of signed-digit DSP processors
  288. A systematic methodology for designing multilevel systolic architectures
  289. Abstract and Concrete Data Type Optimizations at the UML and C/C++ Level for Dynamic Embedded Software
  290. Data and instruction memory performance and energy optimization technique
  291. A Survey of Coarse-Grain Reconfigurable Architectures and Cad Tools
  292. A Survey of Existing Fine-Grain Reconfigurable Architectures and CAD tools
  293. A low-energy FPGA: architecture design and software-supported design flow
  294. A Methodology for Partitioning DSP Applications in Hybrid Reconfigurable Systems
  295. A Petri net approach to the design of processor array architectures
  296. A systematic methodology for designing multilevel systolic architectures
  297. Low-power design of array architectures