All Stories

  1. Making Peer-to-Peer Federated Learning Work Smoothly Across Different Devices
  2. Approximate Computing Survey, Part II: Application-Specific & Architectural Approximation Techniques and Applications
  3. Approximate Computing Survey, Part I: Terminology and Software & Hardware Approximation Techniques
  4. CollectiveHLS: A Collaborative Approach to High-Level Synthesis Design Optimization
  5. Mixed-precision Neural Networks on RISC-V Cores: ISA extensions for Multi-Pumped Soft SIMD Operations
  6. Data-driven HLS optimization for reconfigurable accelerators
  7. Late Breaking Results: Language-level QoR modeling for High-Level Synthesis
  8. Seamless HW-accelerated AI serving in heterogeneous MEC Systems with AI@EDGE
  9. Beyond RSS: Towards Intelligent Dynamic Memory Management (Work in Progress)
  10. A Framework for the Protection of Critical Infrastructures from Combined Cyber and Physical Threats
  11. The Unexpected Efficiency of Bin Packing Algorithms for Dynamic Storage Allocation in the Wild: An Intellectual Abstract
  12. A Methodology for enhancing Emergency Situational Awareness through Social Media
  13. Hardware Approximate Techniques for Deep Neural Network Accelerators: A Survey
  14. FADE
  15. Process Variability Analysis in Interconnect, Logic, and Arithmetic Blocks of 16-nm FinFET FPGAs
  16. Improving Power of DSP and CNN Hardware Accelerators Using Approximate Floating-point Multipliers
  17. FPGA Acceleration of Short Read Alignment
  18. Improving Performance-Power-Programmability in Space Avionics with Edge Devices: VBN on Myriad2 SoC
  19. EVOLVE
  20. Scale-out beam longitudinal dynamics simulations
  21. A Closed-Loop Controller to Ensure Performance and Temperature Constraints for Dynamic Applications
  22. Cooperative Arithmetic-Aware Approximation Techniques for Energy-Efficient Multipliers
  23. Oops
  24. Energy-Efficient VLSI Implementation of Multipliers with Double LSB Operands
  25. Single- and Multi-FPGA Acceleration of Dense Stereo Vision for Planetary Rovers
  26. PVT-Aware Sensing and Voltage Scaling for Energy Efficient FPGAs
  27. OpenCL-based Virtual Prototyping and Simulation of Many-Accelerator Architectures
  28. Distributed Trade-Based Edge Device Management in Multi-Gateway IoT
  29. A Hierarchical Distributed Runtime Resource Management Scheme for NoC-Based Many-Cores
  30. A Framework Exploiting Process Variability to Improve Energy Efficiency in FPGA Applications
  31. High-Performance Embedded Computing in Space: Evaluation of Platforms for Vision-Based Navigation
  32. Runtime Slack Creation for Processor Performance Variability using System Scenarios
  33. SoftRM
  34. BrainFrame: A node-level heterogeneous accelerator platform for neuron simulations
  35. AEGLE's Cloud Infrastructure for Resource Monitoring and Containerized Accelerated Analytics
  36. Project HIPNOS: Case Study of High Performance Avionics for Active Debris Removal in Space
  37. Energy Efficient Adaptive Approach for Dependable Performance in the presence of Timing Interference
  38. FabSpace 2.0: A platform for application and service development based on Earth Observation data
  39. Spark acceleration on FPGAs: A use case on machine learning in Pynq
  40. An Exploration Framework for Efficient High-Level Synthesis of Support Vector Machines: Case Study on ECG Arrhythmia Detection for Xilinx Zynq SoC
  41. Application performance improvement by exploiting process variability on FPGA devices
  42. A low-complexity control mechanism targeting smart thermostats
  43. HARPA: Tackling physically induced performance variability
  44. A Framework for Interconnection-Aware Domain-Specific Many-Accelerator Synthesis
  45. Parameter Sensitivity in Virtual FPGA Architectures
  46. CF-TUNE: Collaborative Filtering Auto-Tuning for Energy Efficient Many-core Processors
  47. Dataflow Acceleration of scikit-learn Gaussian Process Regression
  48. Optimizing Extended Hodgkin-Huxley Neuron Model Simulations for a Xeon/Xeon Phi Node
  49. Agora: Agent and market-based resource management for many-core systems
  50. Computation offloading and resource allocation for low-power IoT edge devices
  51. A 56 Gbaud reconfigurable FPGA feed-forward equalizer for optical datacenter networks with flexible baudrate- and modulation-format
  52. A Flexible, High-Performance FPGA Implementation of a Feed-Forward Equalizer for Optical Interconnects up to 112 Gb/s
  53. A Customizable Framework for Application Implementation onto 3-D FPGAs
  54. Design-Efficient Approximate Multiplication Circuits Through Partial Product Perforation
  55. Improving Dynamic Memory Allocation on Many-Core Embedded Systems With Distributed Shared Memory
  56. A survey on reconfigurable accelerators for cloud computing
  57. HW/SW Codesign and FPGA Acceleration of Visual Odometry Algorithms for Rover Navigation on Mars
  58. An Integrated Exploration and Virtual Platform Framework for Many-Accelerator Heterogeneous Systems
  59. A Systematic Methodology for Optimization of Applications Utilizing Concurrent Data Structures
  60. A framework for exploring alternative fault-tolerant schemes targeting 3-D reconfigurable architectures
  61. Performance and energy evaluation of spark applications on low-power SoCs
  62. An OpenCL-based framework for rapid virtual prototyping of heterogeneous architectures
  63. Performance-power exploration of software-defined big data analytics: The AEGLE cloud backend
  64. Near-Static Shading Exploration for Smart Photovoltaic Module Topologies Based on Snake-like Configurations
  65. Accuracy of Quasi-Monte Carlo technique in failure probability estimations
  66. ANT3D: Simultaneous Partitioning and Placement for 3-D FPGAs based on Ant Colony Optimization
  67. First impressions from detailed brain model simulations on a Xeon/Xeon-Phi node
  68. Parallel application placement onto 3-D reconfigurable architectures
  69. ECG signal analysis and arrhythmia detection on IoT wearable medical devices
  70. Customization methodology for implementation of streaming aggregation in embedded systems
  71. Performance analysis of accelerated biophysically-meaningful neuron simulations
  72. Efficient variability analysis of arithmetic units using linear regression techniques
  73. Runtime Interval Optimization and Dependable Performance for Application-Level Checkpointing
  74. Runtime management of adaptive MPSoCs for graceful degradation
  75. Capturing True Workload Dependency of BTI-induced Degradation in CPU Components
  76. A Survey on FEC Codes for 100 G and Beyond Optical Networks
  77. A Co-Design Approach For Rapid Prototyping Of Image Processing On SoC FPGAs
  78. The VINEYARD Approach: Versatile, Integrated, Accelerator-Based, Heterogeneous Data Centres
  79. Deploying and monitoring hadoop MapReduce analytics on single-chip cloud computer
  80. Distributed QoS management for internet of things under resource constraints
  81. An Evolutionary Algorithm for Netlist Partitioning Targeting 3-D FPGAs
  82. A MapReduce scratchpad memory for multi-core cloud computing applications
  83. Advancing Integrated and Personalized Healthcare Services, the AEGLE Approach
  84. Job-Arrival Aware Distributed Run-Time Resource Management on Intel SCC Manycore Platform
  85. Rapid prototyping and Design Space Exploration methodologies for many-accelerator systems
  86. High-Level-Synthesis extensions for scalable Single-Chip Many-Accelerators on FPGAs
  87. Preface
  88. Tackling Performance Variability Due to RAS Mechanisms with PID-Controlled DVFS
  89. Platform-aware dynamic data type refinement methodology for radix tree Data Structures
  90. Many-core CPUs can deliver scalable performance to stochastic simulations of large-scale biochemical reaction networks
  91. Hybrid approximate multiplier architectures for improved power-accuracy trade-offs
  92. Mitigating Memory-Induced Dark Silicon in Many-Accelerator Architectures
  93. HARPA: Solutions for dependable performance under physically induced performance variability
  94. AEGLE: A big bio-data analytics framework for integrated health-care services
  95. Efficient Reliability Analysis of Processor Datapath using Atomistic BTI Variability Models
  96. Classification Framework for Analysis and Modeling of Physically Induced Reliability Violations
  97. Demonstrating HW–SW Transient Error Mitigation on the Single-Chip Cloud Computer Data Plane
  98. Placement of Linked Dynamic Data Structures over Heterogeneous Memories in Embedded Systems
  99. GENESIS
  100. SPARTAN/SEXTANT/COMPASS: Advancing Space Rover Vision via Reconfigurable Platforms
  101. Trusted Computing for Embedded Systems
  102. Applied Reconfigurable Computing
  103. Dynamic Memory Management for Embedded Systems
  104. Reconfigurable Computing for Analytics Acceleration of Big Bio-Data: The AEGLE Approach
  105. Using Chaos Theory based workload analysis to perform Dynamic Frequency Scaling on MPSoCs
  106. An Energy Efficient Message Passing Synchronization Algorithm for Concurrent Data Structures in Embedded Systems
  107. SWAN-iCARE Project: On the Efficiency of FPGAs Emulating Wearable Medical Devices for Wound Management and Monitoring
  108. A Novel Concept for Adaptive Signal Processing on Reconfigurable Hardware
  109. TEAChER: TEach AdvanCEd Reconfigurable Architectures and Tools
  110. Effective Learning and Filtering of Faulty Heart-Beats for Advanced ECG Arrhythmia Detection using MIT-BIH Database
  111. Plug&Chip
  112. A Framework for Supporting Adaptive Fault-Tolerant Solutions
  113. Linear regression techniques for efficient analysis of transistor variability
  114. A MapReduce framework implementation for Network-on-Chip platforms
  115. Heap Management for Trusted Operating Environments
  116. Reconfigurable FEC codes for software-defined optical transceivers
  117. A Reconfigurable MapReduce accelerator for multi-core all-programmable SoCs
  118. Introduction
  119. Intermediate Variable Removal from Dynamic Applications
  120. Systematic Placement of Dynamic Objects Across Heterogeneous Memory Hierarchies
  121. Dynamic Data Types Optimization in Multimedia and Communication Applications
  122. Analysis and Characterization of Dynamic Multimedia Applications
  123. Profiling and Analysis of Dynamic Applications
  124. Dynamic Memory Management Optimization for Multimedia Applications
  125. Systematic Exploration of Power-Aware Scenarios for IEEE 802.11ac WLAN Systems
  126. Performance and power consumption evaluation of concurrent queue implementations in embedded systems
  127. Evaluation of message passing synchronization algorithms in embedded systems
  128. Optimal mapping of inferior olive neuron simulations on the Single-Chip Cloud Computer
  129. A framework for rapid evaluation of heterogeneous 3-D NoC architectures
  130. Understanding timing impact of BTI/RTN with massively threaded atomistic transient simulations
  131. A Framework for Mapping Dynamic Virtual Kernels onto Heterogeneous Reconfigurable Platforms
  132. A Framework for Customizing Virtual 3-D Reconfigurable Platforms at Run-Time
  133. A Low-Latency Algorithm and FPGA Design for the Min-Search of LDPC Decoders
  134. The Enexal Bauxite Residue Treatment Process: Industrial Scale Pilot Plant Results
  135. Designing 2D and 3D Network-on-Chip Architectures
  136. A novel 3-D FPGA architecture targeting communication intensive applications
  137. Hardware Accelerated Rician Denoise Algorithm for High Performance Magnetic Resonance Imaging
  138. A HW/SW Framework Emulating Wearable Devices For Remote Wound Monitoring and Management
  139. Effective Platform-Level Exploration for Heterogeneous Multicores Exploiting Simulation-Induced Slacks
  140. Power-aware dynamic memory management on many-core platforms utilizing DVFS
  141. A low-cost fault tolerant solution targeting commercial FPGA devices
  142. SPARTAN: Developing a Vision System for Future Autonomous Space Exploration Robots
  143. The SYSMANTIC NoC Design and Prototyping Framework
  144. NoC-Based System Integration
  145. Projects on Network-on-Chip
  146. NoC Verification and Testing
  147. Communication Architecture
  148. Middleware Memory Management in NoC
  149. Power and Thermal Effects and Management
  150. NoC Modeling and Topology Exploration
  151. The Spidergon STNoC
  152. On Designing 3-D Platforms
  153. Network-on-Chip Technology: A Paradigm Shift
  154. A platform-independent runtime methodology for mapping multiple applications onto FPGAs through resource virtualization
  155. A low-complexity implementation of QC-LDPC encoder in reconfigurable logic
  156. Automatic implementation of low-complexity QC-LDPC encoders
  157. Automatic implementation of low-complexity QC-LDPC encoders
  158. System scenarios-based architecture level exploration of SDR application using a network-on-chip simulation framework
  159. A Process-based Reconfigurable SystemC Module for simulation speedup
  160. JITPR
  161. SWAN-iCare: A smart wearable and autonomous negative pressure device for wound monitoring and therapy
  162. Arterial Dissection
  163. On Supporting Adaptive Fault Tolerant at Run-Time with Virtual FPGAs
  164. HVSoCs: A Framework for Rapid Prototyping of 3-D Hybrid Virtual System-on-Chips
  165. Hypervised Transient SPICE Simulations of Large Netlists & Workloads on Multi-Processor Systems
  166. Performance Evaluation of Embedded Processor in MapReduce Cloud Computing Applications
  167. Distributed run-time resource management for malleable applications on many-core platforms
  168. Run-Time Measurement of Harvested Energy for Autarkic Sensor Operation
  169. Compiler-in-the-loop exploration during datapath synthesis for higher quality delay-area trade-offs
  170. High-level customization framework for application-specific NoC architectures
  171. Enabling Efficient System Configurations for Dynamic Wireless Applications Using System Scenarios
  172. Adaptive dynamic memory allocators by estimating application workloads
  173. Systematic design and evaluation of a scalable reconfigurable multiplier scheme for HLS environments
  174. A low-cost fault tolerant solution targeting to commercial FPGA devices
  175. On Supporting Efficient Partial Reconfiguration with Just-In-Time Compilation
  176. A novel framework for exploring 3-D FPGAs with heterogeneous interconnect fabric
  177. Scalable Multi-core Architectures
  178. A Systematic Methodology for Reliability Improvements on SoC-Based Software Defined Radio Systems
  179. Framework for performing rapid evaluation of 3D SoCs
  180. Design and experimentation with low-power morphable multipliers
  181. Power, performance and area prediction of 3D ICs during early stage design exploration in 45nm
  182. Low-Power Reconfigurable Component Utilization in a High-Level Synthesis Flow
  183. Enabling efficient system configurations for dynamic wireless baseband engines using system scenarios
  184. Application-Specific Multi-Threaded Dynamic Memory Management
  185. A Framework for Architecture-Level Exploration of Communication Intensive Applications onto 3-D FPGAs
  186. A Methodology and Tool Framework for Supporting Rapid Exploration of Memory Hierarchies in FPGAs
  187. Thermal optimization for micro-architectures through selective block replication
  188. Custom Microcoded Dynamic Memory Management for Distributed On-Chip Memory Organizations
  189. FILESPPA: Fast Instruction Level Embedded System Power and Performance Analyzer
  190. CAD tools for designing 3D integrated systems
  191. Keynote speech 2: Reconfigurable systems and 3D architectures
  192. A reconfigurable IP characterization technique improving high-level synthesis results
  193. A novel methodology for architecture-level exploration of 3D SoCs
  194. A standard-cell library suite for deep-deep sub-micron CMOS technologies
  195. High Performance and Area Efficient Flexible DSP Datapath Synthesis
  196. On Supporting Rapid Thermal Analysis
  197. Three Dimensional System Integration
  198. A High Level Synthesis Exploration Framework with Iterative Design Space Partitioning
  199. Mapping Embedded Applications on MPSoCs: The MNEMEE Approach
  200. The MOSART Mapping Optimization for Multi-Core ARchiTectures
  201. A Framework for Architecture-Level Exploration of 3-D FPGA Platforms
  202. A Temperature-Aware Time-Dependent Dielectric Breakdown Analysis Framework
  203. Multiple Vdd on 3D NoC architectures
  204. A Methodology for Alleviating the Performance Degradation of TMR Solutions
  205. BIT-width exploration over 3D architectures using high-level synthesis
  206. Introduction to Three-Dimensional Integration
  207. Towards Supporting Fault-Tolerance in FPGAs
  208. A High-Level Mapping Algorithm Targeting 3D NoC Architectures with Multiple Vdd
  209. High-Level Synthesis Methodologies for Delay-Area Optimized Coarse-Grained Reconfigurable Coprocessor Architectures
  210. Systematic Exploration of Energy-Efficient Application-Specific Network-on-Chip Architectures
  211. Efficient High Level Synthesis Exploration Methodology Combining Exhaustive and Gradient-Based Pruned Searching
  212. Custom multi-threaded Dynamic Memory Management for Multiprocessor System-on-Chip platforms
  213. Mapping Optimisation for Scalable Multi-core ARchiTecture: The MOSART Approach
  214. Mapping Embedded Applications on MPSoCs: The MNEMEE Approach
  215. Software metadata: Systematic characterization of the memory behaviour of dynamic applications
  216. Designing efficient DSP datapaths through compiler-in-the-loop exploration methodology
  217. A NOVEL ALLOCATION METHODOLOGY FOR PARTIAL AND DYNAMIC BITSTREAM GENERATION FOR FPGA ARCHITECTURES
  218. Construction of dual mode components for reconfiguration aware high-level synthesis
  219. VLSI-SoC: Design Methodologies for SoC and SiP
  220. Fast Instruction Memory Hierarchy Power Exploration for Embedded Systems
  221. A framework for automatic parallelization, static and dynamic memory optimization in MPSoC platforms
  222. A Temperature-Aware Placement and Routing Algorithm Targeting 3D FPGAs
  223. A Framework for Enabling Fault Tolerance in Reconfigurable Architectures
  224. Multi-granularity NoC Simulation Framework for Early Phase Exploration of SDR Hardware Platforms
  225. MNEMEE
  226. Dynamic Data Type Optimization and Memory Assignment Methodologies
  227. Application-Specific Temperature Reduction Systematic Methodology for 2D and 3D Networks-on-Chip
  228. Compilation Technique for Loop Overhead Minimization
  229. Three dimensional FPGA architectures: A shift paradigm for energy-performance efficient DSP implementations
  230. Node resource management for DSP applications on 3D Network-on-Chip architecture
  231. Optimization methodology of dynamic data structures based on genetic algorithms for multimedia embedded systems
  232. A software-supported methodology for exploring interconnection architectures targeting 3-D FPGAs
  233. Three-Dimensional Networks-on-Chip Architectures
  234. An Efficient Approach for Managing Power Consumption Hotspots Distribution on 3D FPGAs
  235. A Power-Aware Placement and Routing Algorithm Targeting 3D FPGAs
  236. Aortic Function in Beta-Thalassemia Major
  237. Exploration methodology of dynamic data structures in multimedia and network applications for embedded platforms
  238. Designing a novel high-performance FPGA architecture for data intensive applications
  239. Mapping DSP Applications onto High-Performance Architectural Templates with Inlined Flexibility
  240. Designing a General-Purpose Interconnection Architecture for Field Programmable Gate Arrays
  241. Enabling run-time memory data transfer optimizations at the system level with automated extraction of embedded software metadata information
  242. Architecture-Level Exploration of Alternative Interconnection Schemes Targeting 3D FPGAs: A Software-Supported Methodology
  243. A software-supported methodology for designing high-performance 3D FPGA architectures
  244. Implementing cellular automata modeled applications on network-on-chip platforms
  245. Systematic methodology for exploration of performance – Energy trade-offs in network applications using Dynamic Data Type refinement
  246. Middleware Design Optimization of Wireless Protocols Based on the Exploitation of Dynamic Input Patterns
  247. Preface of Special Issue on VLSI Design and Test
  248. Preface
  249. Fine- and Coarse-Grain Reconfigurable Computing
  250. A Novel Methodology for Temperature-Aware Placement and Routing of FPGAs
  251. Optimization of dynamic data structures in multimedia embedded systems using evolutionary computation
  252. Application - specific NoC platform design based on System Level Optimization
  253. Efficient Power Management Strategy of FPGAs Using a Novel Placement Technique
  254. An Estimation Methodology for Designing Instruction Cache Memory of Embedded Systems
  255. Reducing memory fragmentation in network applications with dynamic memory allocators optimized for performance
  256. Behavioral-Level Performance and Power Exploration of Data-Intensive Applications Mapped on Programmable Processors
  257. Systematic dynamic memory management design methodology for reduced memory footprint
  258. Efficient system-level prototyping of power-aware dynamic memory managers for embedded systems
  259. Wire Segment Length and Switch Box Co-Optimization for FPGA Architectures
  260. Energy-efficient dynamic memory allocators at the middleware level of embedded systems
  261. A novel methodology for designing high-performance and low-energy FPGA routing architecture
  262. Designing Alternative FPGA Implementations Using Spatial Data from Hardware Resources
  263. Circuits Techniques for Dynamic Power Reduction
  264. A method for partitioning applications in hybrid reconfigurable architectures
  265. Editorial: Power and timing modelling, optimisation and simulation
  266. Reducing Memory Fragmentation with Performance-Optimized Dynamic Memory Allocators in Network Applications
  267. Improving the Memory Bandwidth Utilization Using Loop Transformations
  268. International EMS systems: Greece
  269. Circuits Techniques for Dynamic Power Reduction
  270. A Novel Data-Path for Accelerating DSP Kernels
  271. Design of Energy Efficient Wireless Networks Using Dynamic Data Type Refinement Methodology
  272. Power, Performance and Area Exploration for Data Memory Assignment of Multimedia Applications
  273. Designing CMOS Circuits for Low Power
  274. Motivation, Context and Objectives
  275. Logic Level Power Optimization
  276. Sources of Power Dissipation in CMOS Circuits
  277. THE DESIGN OF A RIPPLE CARRY ADIABATIC ADDER
  278. Integrated Circuit Design
  279. Run-Time Power Management for Low and Medium Bit-Rate Digital Receivers
  280. Mapping iterative algorithims on regular processor arrays without using uniform recurrent equations
  281. Ateleological Developments of "Design-Decisions-Independent" Information Systems
  282. Designing Heterogeneous FPGAs with Multiple SBs
  283. System-Level Application-Specific NoC Design for Network and Multimedia Applications
  284. Direct Memory Access Optimization in Wireless Terminals for Reduced Memory Latency and Energy Consumption
  285. Systematic design of novel architectures for implementation of Radon Transform
  286. Designing efficient redundant arithmetic processors for DSP applications
  287. Design methodology for direct mapping of iterative algorithms on array architectures
  288. Design methodology of mapping iterative algorithms on piecewise regular processor arrays
  289. Methodology for the design of signed-digit DSP processors
  290. A Partitioning Methodology for Accelerating Applications in Hybrid Reconfigurable Platforms
  291. A window-based color quantization technique and its embedded implementation
  292. A novel division algorithm for parallel and sequential processing
  293. Methodology for the design of signed-digit DSP processors
  294. A systematic methodology for designing multilevel systolic architectures
  295. Abstract and Concrete Data Type Optimizations at the UML and C/C++ Level for Dynamic Embedded Software
  296. Data and instruction memory performance and energy optimization technique
  297. A Survey of Coarse-Grain Reconfigurable Architectures and Cad Tools
  298. A Survey of Existing Fine-Grain Reconfigurable Architectures and CAD tools
  299. A low-energy FPGA: architecture design and software-supported design flow
  300. A Methodology for Partitioning DSP Applications in Hybrid Reconfigurable Systems
  301. A Petri net approach to the design of processor array architectures
  302. A systematic methodology for designing multilevel systolic architectures
  303. Low-power design of array architectures