What is it about?
Designing robust performance models for modern complex digital circuits in the face of rapidly accelerating process variations is a critical yet demanding task. This paper introduces an efficient statistical performance modeling approach for VLSI digital circuits that incurs minimal computational expense. The fundamental concept involves capitalizing on knowledge gained from circuit modeling in one technology node to streamline the modeling process in another. This is achieved by merging previously established statistical models of process technology with a limited set of simulation data from a subsequent process technology through transfer learning. Comprehensive experiments conducted across diverse technology nodes demonstrate that the proposed framework is robust, precise, efficient in data usage, and computationally superior to other cutting-edge performance modeling techniques.
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Why is it important?
Our research demonstrates that PVT-aware circuit behavior can be effectively transferred to subsequent or more advanced technology nodes, significantly reducing data requirements by several orders of magnitude while maintaining high modeling efficiency. We developed highly efficient Dense Neural Networks using transfer learning across various technology nodes. This methodology speeds up 10000 times compared to SPICE and offers up to a 10x cost reduction relative to other state-of-the-art modeling techniques.
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This page is a summary of: Transfer Learning Enabled Modeling Paradigm for PVT-aware Circuit Performance Estimation, ACM Transactions on Design Automation of Electronic Systems, August 2024, ACM (Association for Computing Machinery),
DOI: 10.1145/3689435.
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