All Stories

  1. Transfer Learning Enabled Modeling Paradigm for PVT-aware Circuit Performance Estimation

    Article • ACM Transactions on Design Automation of Electronic Systems, August 2024, ACM (Association for Computing Machinery)

    Zia Abbas, Deepthi Amuru

  2. A label-free sensing of creatinine using radio frequency-driven lab-on-chip (loc) system

    Article • Engineering Research Express, August 2024, Institute of Physics Publishing

    Zia Abbas

  3. A 275 pW, 0.5 V supply insensitive gate-leakage based current/voltage reference circuit for a wide temperature range of −55 to 100 °C without using amplifiers and resistors

    Article • Microelectronics Journal, August 2024, Elsevier

    Zia Abbas

  4. Qualitative data augmentation for performance prediction in VLSI circuits

    Article • Integration, July 2024, Elsevier

    Zia Abbas

  5. A Theoretical Study of the Representational Power of Weighted Randomised Univariate Regression Tree Ensembles

    Article • Journal of Information & Knowledge Management, April 2024, World Scientific Pub Co Pte Lt

    Zia Abbas

  6. AI/ML algorithms and applications in VLSI design and technology

    Article • Integration, November 2023, Elsevier

    Zia Abbas, Deepthi Amuru

  7. Approximate Toom–Cook FFT with sparsity aware error tuning in a shared memory architecture

    Article • Integration, March 2023, Elsevier

    Zia Abbas

  8. A Novel Smart Belt for Anxiety Detection, Classification, and Reduction Using IIoMT on Students’ Cardiac Signal and MSY

    Article • Bioengineering, December 2022, MDPI AG

    Zia Abbas, Dr. Md Belal Bin Heyat

  9. An End-to-End Cardiac Arrhythmia Recognition Method with an Effective DenseNet Model on Imbalanced Datasets Using ECG Signal

    Article • Computational Intelligence and Neuroscience, September 2022, Hindawi Publishing Corporation

    Zia Abbas, Dr. Md Belal Bin Heyat

  10. A 9.5nW, 0.55V Supply, CMOS Current Reference for Low Power Biomedical Applications

    Article • IEEE Transactions on Circuits & Systems II Express Briefs, September 2022, Institute of Electrical & Electronics Engineers (IEEE)

    Zia Abbas

  11. Implementation of TRNG with SHA-3 for hardware security

    Article • Microelectronics Journal, May 2022, Elsevier

    Zia Abbas

  12. A 419pW Process-Invariant Temperature Sensor for Ultra-Low Power Microsystems

    Article • May 2021, Institute of Electrical & Electronics Engineers (IEEE)

    Zia Abbas

  13. Low Power PVT-Aware Transistor Sizing and Approximate Design Generation for Standard Cells Using Swarm Intelligence

    Article • May 2021, Institute of Electrical & Electronics Engineers (IEEE)

    Zia Abbas

  14. Algorithm Driven Power-Timing Optimization Methodology for CMOS Digital Circuits Considering PVTA Variations

    Article • May 2021, Institute of Electrical & Electronics Engineers (IEEE)

    Zia Abbas

  15. PVT and Aging Degradation Invariant Automated Optimization Approach for CMOS Low-Power High-Performance VLSI Circuits

    Article • April 2021, Institute of Electrical & Electronics Engineers (IEEE)

    Zia Abbas

  16. Transistor Sizing based PVT-Aware Low Power Optimization using Swarm Intelligence

    Article • February 2021, Institute of Electrical & Electronics Engineers (IEEE)

    Zia Abbas

  17. ATM: Approximate Toom-Cook Multiplication for Speech Processing Applications

    Article • October 2020, Institute of Electrical & Electronics Engineers (IEEE)

    Zia Abbas, Deepthi Amuru

  18. An Efficient Gradient Boosting Approach for PVT Aware Estimation of Leakage Power and Propagation Delay in CMOS/FinFET Digital Cells

    Article • October 2020, Institute of Electrical & Electronics Engineers (IEEE)

    Zia Abbas, Deepthi Amuru

  19. Low Quiescent Current, Capacitor-Less LDO with Adaptively Biased Power Transistors and Load Aware Feedback Resistance

    Article • October 2020, Institute of Electrical & Electronics Engineers (IEEE)

    Zia Abbas

  20. 67ppm/°C, 66nA PVT Invariant Curvature Compensated Current Reference for Ultra-Low Power Applications

    Article • October 2020, Institute of Electrical & Electronics Engineers (IEEE)

    Zia Abbas

  21. A Sub-nW, 8T Current Reference Consuming Constant Power w.r.t Process & Temperature

    Article • August 2020, Institute of Electrical & Electronics Engineers (IEEE)

    Zia Abbas

  22. A Compact, Power Efficient, Self-Adaptive and PVT Invariant CMOS Relaxation Oscillator

    Article • July 2020, Institute of Electrical & Electronics Engineers (IEEE)

    Zia Abbas

  23. 3.75ppm/°C, -91dB PSRR, 27nW, 0.9V PVT Invariant Voltage Reference for Implantable Biomedical Applications

    Article • January 2020, Institute of Electrical & Electronics Engineers (IEEE)

    Zia Abbas

  24. Optimal Power-Area Polar Decoder Design based on Iterative Decomposition Technique

    Article • December 2019, Institute of Electrical & Electronics Engineers (IEEE)

    Zia Abbas

  25. A Highly Accurate Machine Learning Approach to Modelling PVT Variation Aware Leakage Power in FinFET Digital Circuits

    Article • November 2019, Institute of Electrical & Electronics Engineers (IEEE)

    Zia Abbas

  26. A Memetic Algorithm Based PVT Variation-Aware Robust Transistor Sizing Scheme for Power-Delay Optimal Digital Standard Cell Design

    Article • November 2019, Institute of Electrical & Electronics Engineers (IEEE)

    Zia Abbas

  27. A 47nW, 0.7-3.6V wide Supply Range, Resistor Based Temperature Sensor for IoT Applications

    Article • October 2019, Institute of Electrical & Electronics Engineers (IEEE)

    Zia Abbas

  28. A High PSRR, Stable CMOS Current Reference using Process Insensitive TC of Resistance for Wide Temperature Applications

    Article • May 2019, Institute of Electrical & Electronics Engineers (IEEE)

    Zia Abbas

  29. PVT Variations Aware Robust Transistor Sizing for Power-Delay Optimal CMOS Digital Circuit Design

    Article • May 2019, Institute of Electrical & Electronics Engineers (IEEE)

    Zia Abbas

  30. Robust Transistor Sizing for Improved Performances in Digital Circuits using Optimization Algorithms

    Article • March 2019, Institute of Electrical & Electronics Engineers (IEEE)

    Zia Abbas

  31. LEADER: Leakage Currents Estimation Technique for Aging Degradation Aware 16 nm CMOS Circuits

    Article • January 2019, Springer Science + Business Media

    Zia Abbas

  32. Optimal Transistor Sizing of Full-Adder Block to Reduce Standby Leakage Power

    Article • January 2019, Springer Science + Business Media

    Zia Abbas

  33. Statistical Variation Aware Leakage and Total Power Estimation of 16 nm VLSI Digital Circuits Based on Regression Models

    Article • January 2019, Springer Science + Business Media

    Zia Abbas, Deepthi Amuru

  34. Voltage Level Adapter Design for High Voltage Swing Applications in CMOS Differential Amplifier

    Article • January 2019, Springer Science + Business Media

    Zia Abbas

  35. Geometry Scaling Impact on Leakage Currents in FinFET Standard Cells Based on a Logic-Level Leakage Estimation Technique

    Article • January 2018, Springer Science + Business Media

    Zia Abbas

  36. THERMAL STUDY OF LAB ON CHIP (LOC) SYSTEM FOR PCR REACTION APPLICATIONS

    Article • January 2018, Begell House

    Zia Abbas

  37. Yield-driven power-delay-optimal CMOS full-adder design complying with automotive product specifications of PVT variations and NBTI degradations

    Article • Journal of Computational Electronics, August 2016, Springer Science + Business Media

    Zia Abbas

  38. MS 16 MINISYMPOSIUM: METHODS FOR ADVANCED MULTI-OBJECTIVE OPTIMIZATION FOR eDFY OF COMPLEX NANO-SCALE CIRCUITS

    Article • January 2016, Springer Science + Business Media

    Zia Abbas

  39. Statistical Variation Aware ANN and SVM Model Generation for Digital Standard Cells

    Article • January 2016, Springer Science + Business Media

    Zia Abbas

  40. Optimal transistor sizing for maximum yield in variation-aware standard cell design

    Article • International Journal of Circuit Theory and Applications, October 2015, Wiley

    Zia Abbas

  41. Optimal NBTI degradation and PVT variation resistant device sizing in a full adder cell

    Article • September 2015, Institute of Electrical & Electronics Engineers (IEEE)

    Zia Abbas

  42. Variability aware modeling of SEU induced failure probability of logic circuit paths in static conditions

    Article • September 2015, Institute of Electrical & Electronics Engineers (IEEE)

    Zia Abbas

  43. A Voltage-Based Leakage Current Calculation Scheme and its Application to Nanoscale MOSFET and FinFET Standard-Cell Designs

    Article • IEEE Transactions on Very Large Scale Integration (VLSI) Systems, December 2014, Institute of Electrical & Electronics Engineers (IEEE)

    Zia Abbas

  44. Impact of technology scaling on leakage power in nano-scale bulk CMOS digital standard cells

    Article • Microelectronics Journal, February 2014, Elsevier

    Zia Abbas

  45. Sizing and optimization of low power process variation aware standard cells

    Article • October 2013, Institute of Electrical & Electronics Engineers (IEEE)

    Zia Abbas

  46. Design centering/yield optimization of power aware band pass filter based on CMOS current controlled current conveyor (CCCII+)

    Article • Microelectronics Journal, April 2013, Elsevier

    Zia Abbas

  47. Yield optimization for low power current controlled current conveyor

    Article • August 2012, Institute of Electrical & Electronics Engineers (IEEE)

    Zia Abbas

  48. A novel logic level calculation model for leakage currents in digital nano-CMOS circuits

    Article • July 2011, Institute of Electrical & Electronics Engineers (IEEE)

    Zia Abbas

  49. Experimental use of electronic nose for analysis of volatile organic compound (VOC)

    Article • March 2009, Institute of Electrical & Electronics Engineers (IEEE)

    Zia Abbas