What is it about?
Gem5 is one of the most widespread architectural simulators. One of its disadvantages is the lack of a proper virtual memory system representation when it is used in system-call emulation mode. In this paper, we describe the additions we made to the gem5 source code in order to integrate this shortage, using the RISC-V as reference ISA. Moreover, we open-sourced the code, allowing other researchers to use and extend this work for their purposes.
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Photo by Alexandre Debiève on Unsplash
Why is it important?
RISC-V is emerging as a promising ISA choice for developers, researchers, and companies. Its open-source nature makes it particularly attractive to experiment and prototype. Architectural simulation is a fundamental step in this process, but it needs to be as accurate as possible. Our work allows users to increase simulation accuracy when it comes to page walking and virtual-to-physical address translation.
Perspectives
It is always a pleasure to contribute to the community with open-source, free tools. We all enjoyed working on this project and we hope our impact can make the difference for researchers working in this field.
Biagio Peccerillo
Universita degli Studi di Siena
Read the Original
This page is a summary of: Integration of RISC-V Page Table Walk in gem5 SE Mode, January 2024, ACM (Association for Computing Machinery),
DOI: 10.1145/3642921.3642926.
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