What is it about?
Instruction set architectures (ISAs) are the integral contract between hardware and software. Simply a written definition, they can have real consequences on the performance, energy efficiency, and die area of a CPU. We compare two such ISAs, Arm's AArch64 and RISC-V, with a focus on theoretical performance limits (what is the least amount of time a program could complete in using this ISA?) before approximating runtimes with certain physical limitations. We use these experiments to direct discussion about some of the differences in instruction complexity and the current state of the ecosystem surrounding each ISA.
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Why is it important?
Arm has recently made the transition into high performance computing (HPC) applications after dominating the embedded systems market for many years. RISC-V is currently making inroads in this space but with lots of scepticism about whether it could make the same transition to HPC. We aim to provide some of the first experimental data, focussing on common HPC style workloads to expose similarities and differences between them, and shine some light on the potential future of RISC-V.
Perspectives
It has been interesting to see the communities in this area take such strong and convicted sides with these two ISAs. Hopefully, this research can provide robust data for further discussions to take place.
Daniel Weaver
University of Bristol
Read the Original
This page is a summary of: An Empirical Comparison of the RISC-V and AArch64 Instruction Sets, November 2023, ACM (Association for Computing Machinery),
DOI: 10.1145/3624062.3624233.
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