What is it about?
Wafer-scale chips put nearly a million processors on one silicon wafer, but each wafer typically has a few dozen manufacturing defects. Today’s chips switch off whole rows and columns containing them, losing tens of thousands of working processors. Earlier fault-tolerant routing methods route around the defects instead, but most need far more memory than each processor has. DLR splits the nearly intact chip into defect-free rectangles, keeping every working processor in use with only about 100 bytes of routing information each.
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Why is it important?
A wafer-scale chip integrates a huge amount of SRAM and computing power on monolithic silicon. Keeping data on-chip gives it enormous bandwidth, making it a promising platform for AI models. But unlike ordinary chips, which can simply be discarded when defective, defects must be tolerated on wafer-scale-chip. DLR does this without switching off healthy processors, reclaiming the tens of thousands that today’s chips lose, wherever the defects fall.
Perspectives
Existing wafer-scale chips, such as the Cerebras WSE, tolerate defects with very small cores, spares, and diagonal links that rebuild a mesh homeomorphic to a defect-free one, so programmers still see a regular grid. But if we want each core to do more and each link to offer more bandwidth, spare cores and extra links become costly, and different defect-tolerance mechanisms may be needed. DLR offers one: it handles defects through routing rather than spare hardware. As an early study of defect-tolerant routing at wafer scale, I hope this work opens the door to a wider range of wafer-scale chip architectures.
Yi-Chieh Wang
University of Edinburgh
Read the Original
This page is a summary of: DLR: Efficient Defect-Tolerant Routing at Wafer Scale, April 2027, ACM (Association for Computing Machinery),
DOI: 10.1145/3845814.3850067.
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