What is it about?
We propose a method named SIMTAM, to detect bugs in FPGA timing simulation tools based on timing area mutation. By creating a sleep region in the timing concept, we can generate diversity test cases with complex timing relationships for testing FPGA timing simulation tool bugs. In five months, SIMTAM reported 16 bugs to developers in two popular timing simulation tools Iverilog and Vivado; ten of which are confirmed.
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Why is it important?
This paper presents the Simulation Tools Testing Via Timing Area Mutation for FPGAs. Timing analysis is important for chip designing. However, bugs in timing simulation tools can lead to inaccurate results, potentially causing designers to miss critical issues in chip performance.
Perspectives
This article helps me and my collaborators to have a clearer understanding of the concepts of timing simulation and chip design process. In addition, we call on more people to pay attention to the field of software and hardware integration. This is a key field. Smart manufacturing and re-industrialization cannot be separated from the coordination of software and hardware.
zhihao xu
Southeast University
Read the Original
This page is a summary of: SIMTAM: Generation Diversity Test Programs for FPGA Simulation Tools Testing Via Timing Area Mutation, ACM Transactions on Design Automation of Electronic Systems, November 2024, ACM (Association for Computing Machinery),
DOI: 10.1145/3705730.
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