3D IC Devices, Technologies, and Manufacturing

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Preface My first exposure to the semiconductor industry was 1975 in Microwave Diode Department of Chengdu Guoguang Electric Co. , with my middle school classmates in a month long “learn from workers” program, which was very common for Chinese school kids during the chaotic period of “Culture Revolution” (1966 -1976). The silicon wafer size was 1 inch, and we were making crystal diodes used in radar as microwave detector. The factory had serval process bays, such as diffusion, wet clean, wafer dicing, assembly, and final test. I had observed workers pushed the wafers into the pyrogenic oxidation furnace and was amazed by the barely visible bluish hydrogen flame in it. I still remember the story of hydrogen leakage induced explosion told during safety training. I worked in final test, using a special instrument to test the diode and determine whether it passed or needed to be thrown into the trash bin underneath the tester. Twenty years later, I started my career in semiconductor industry. The wafer size at that time was 200 mm, and technology node was 350 nm. When the first edition of my textbook “Introduction to Semiconductor Manufacturing Technology” was published by Prentice Hall in 2000, the technology had scaled down to 180nm and copper metallization was the state-of-art leading edge technology. Ten years after publication of the first edition, wafer size increased to 300 mm and technology node migrated to 32 nm. New technologies that did not mentioned in the first edition, such as Immersion lithography, double patterning, selective epitaxial growth (SEG) and atomic layer deposition (ALD) were widely used to manufacture IC chips with high-k, metal gate front-end and copper, ultra-low-k backend. It became the main driving force for me to write the second edition of the book. There are many new developments after I have summited the final manuscript of the second edition of “Introduction to Semiconductor Manufacturing Technology” in spring of 2012. Because simply scaling down the feature size of the planar MOSFET can no longer improve the device performance while reduce its power consumption, scientists and engineers have worked on the scaling of the nanometer-scale electronic devices in the third dimension. FinFET is one of proposed device architect that has been used to replace the planar MOSFET. At the same feature size, FinFET technology can improve drive current by increasing effective gate width at on-state while reduce standby leakage by operating at fully deplete regime at off-state. Theoretically, FinFET technology can migrate to next generation technology node by just increasing fin height, without shrinking the feature size. Because it is easier to control the fin height of the FinFET technology with silicon thickness of silicon-on-insulator (SOI) substrate, it was thought that FinFET technology needed SOI wafer. Due to the high cost of SOI wafer and difficulties of fin height control with low-cost bulk silicon wafer, many people regarded FinFET technology as a high-risk approach for 22nm or 20nm technology node, event even as late as 2009. In summer of 2012, Intel announced its 22nm FinFET in Symposium on VLSI Technology. Although FinFET technology had been mentioned in the second edition, which was published by SPIE Press in the end of 2012, it was not elaborates because lack of credible materials of its manufacturing processes. In recent years, manufacturing technology of non-volatile memory (NVM), especially NAND flash memory, have developed rapidly, driven by the demands of data storage of mobile electronics devices, such as smart phone, tablet PC, digital camera/camcorder, etc. Because the limitation of 193nm immersion lithography, multiple patterning is required for manufacturing the planar NAND flash memory chips. The cost of triple patterning or quadruple patterning required by the low-teen nm planar NAND flash will become too high, and scientists and engineers have proposed and developed the alternative vertical NAND or 3D-NAND technology that utilize the gate-all-around vertical transistors to stack multiple memory cells in vertical direction. In 2014, Samsung released solid-state drive (SSD) based on 3D-NAND with 32 stacks of NVM, only seven years since Toshiba published the concept in 2007. The SSD with 48-stack 3D-NAND is also available in the market. With 3D-NAND architecture, one can scale to next generation technology node by increasing the number of stacks, without shrinking the feature size. In the second edition of “Introduction to Semiconductor Manufacturing Technology”, 3D-NAND is mentioned in the last chapter, which discusses future trends. The future becomes reality in a very short time. Other technologies mentioned in the second edition but not described in detail is 3D packaging with through silicon via (TSV). By stacking multiple chips with TSV, one can increase device density without shrink the feature size, which has be limited by the capability of 193nm immersion lithography technology and delay of the implement of extreme ultra-violet (EUV) lithography. TSV has long been applied in CMOS image sensor packaging, which forms the tiny camera assembly used in mobile phones, tablets and laptops. TSV wafer stacking requires very high yield of every wafer that to be stacked, otherwise, the combined final yield will suffer. While foundries are still proposing 2.5D packaging with interposer due to the high cost of TSV 3D packaging, Samsung released the first 3D TSV technology based DDR4 modules for enterprise servers in 2014. The rapid development of the IC manufacturing technologies, especially 3D devices like FinFET 3D-NAND and TSV, gives me enough motivation to update the book. Because it is a little bit too soon to publish the 3rd edition of “Introduction to Semiconductor Manufacturing Technology”, I decided to write a booklet dedicates to 3D devices and their manufacturing process, with the plan that it could later be integrated into the 3rd edition as two new chapters. Many people helped me to acquired information and knowledge needed to write this book; many of them helped me by answering my questions and some of them helped me by asking me questions I had no clear answer at that moment, which motivated me to further study and research: Dick James, Oliver Paterson, Hanming Wu, Jong (John) Chen, Chih-Ming Ke, David Fried, Sandy Wen, Xiaodong Wang, Victor Lim, Byoung-Ho Lee, Ming Lei, Qiang Zhao, Kevin Huang, Jeff Zhang, Wee Teck Chia, Takuji Tada, Jeff Barnum, Christina Wang, Paul MacDonald, Chris Mahr, Brian Duffy, Harsh Shiha, Rohan Gosain, Arun Lobo, Neeraj Khanna, Amir Azordegen, and Cecelia Campochiaro, just to name a few. Figure 1.10(b), Figure 1.10(c) and Figure 2.48 are provided by Coventor. Figures 3.9–3.17, used to describe HKMG FinFET processes, were previously published in TechDesign Forums (http://www.techdesignforums.com/practice/technique/finfet-iedm-tipsheet). These images were generated using Coventor’s SEMulator3D virtual-fabrication software platform. Colin Xiao, Jarry Xiao, Sameet Shriyan, and Shishir Ramprasad helped me proofread the draft and corrected many English errors. Without the supports of my wife, Liu (Lucy) Huang, and sons, Jarry and Colin, it would have been impossible to write and finish this book on time. My generation grew up in China without television. Because the “Culture Revolution”, there were very few movies for kids in China in that period. So hungry for movies, I watched anything that projected on the screen. One of the films I watched many times was “Mechanical Drawing”, an educational film for college students of Chengdu Institute of Radio Engineering, currently University of Electronics Science and Technology of China, where my parents worked as professors. Even today, I can still vividly remember this film taught me how a 3D object can be presented by top view, side view and face view. The 3D concept and its presentation with 2D drawing gave me a tremendous help when I took IC design class in graduate school. Basically IC layout is the top view of mechanical drawing with microscopic scale (maybe it should be called nanoscopic scale now). This knowledge is really useful for me to reconstruct the 3D structures of IC devices and figure out the manufacturing processes by correlate the top view images and cross-section images. I really appreciate the person who showed the film and allow me, an elementary schooler, to watch it with college students.

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