This shareable PDF can be hosted on any platform or network and is fully compliant with publisher copyright.
This publication has not yet been explained in plain language by the author(s). However, you can still read the publication.
If you are one of the authors, claim this publication so you can create a plain language summary to help more people find, understand and use it.
This page is a summary of: Worst-case power supply noise and temperature distribution analysis for 3D PDNs with multiple clock domains, June 2013, Institute of Electrical & Electronics Engineers (IEEE),
DOI: 10.1109/newcas.2013.6573628.
You can read the full text:
The following have contributed to this page
