This shareable PDF can be hosted on any platform or network and is fully compliant with publisher copyright.
This publication has not yet been explained in plain language by the author(s). However, you can still read the publication.
If you are one of the authors, claim this publication so you can create a plain language summary to help more people find, understand and use it.
This page is a summary of: A Pattern Recognition Mezzanine based on Associative Memory and FPGA technology for Level 1 Track Triggers for the HL-LHC upgrade, Journal of Instrumentation, February 2016, Institute of Physics Publishing,
DOI: 10.1088/1748-0221/11/02/c02063.
You can read the full text:
The following have contributed to this page
