What is it about?
Our proposed method is to fine-tune the test stimulus of the chip. Experimental results show that the scan-in test power consumption is significantly reduced while the test stimulus is guaranteed to be compressed.
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Why is it important?
After the internal bits of the test vector and test vectors are sorted by our proposed method, scan-in power consumption and test application time can be significantly reduced. This is very important for test cost reduction.
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This page is a summary of: A double-Hamming-distance-based 2-D reordering method for scan-in power reduction and test pattern compression, Electronics Letters, January 2020, the Institution of Engineering and Technology (the IET),
DOI: 10.1049/el.2019.3225.
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