All Stories

  1. A Highly Hardware Efficient ML-KEM Accelerator with Optimised Architectural Layers
  2. SSAT: Active Authorization Control and User’s Fingerprint Tracking Framework for DNN IP Protection
  3. An Imperceptible and Owner-unique Watermarking Method for Graph Neural Networks
  4. Tracking the Leaker: An Encodable Watermarking Method for Dataset Intellectual Property Protection
  5. VLCP: A High-Performance FPGA-based CNN Accelerator with Vector-level Cluster Pruning
  6. An RRAM-based PUF with Adjustable Programmable Voltage and Multi-Mode Operation
  7. An Efficient Ring Oscillator PUF Using Programmable Delay Units on FPGA
  8. Low-cost stochastic number generator based on MRAM for stochastic computing
  9. HEADiv: A High-accuracy Energy-efficient Approximate Divider with Error Compensation
  10. High-performance STT-MRAM Logic-in-Memory Scheme Utilizing Data Read Features
  11. Capacity-oriented High-performance NV-TCAM Leveraging Hybrid MRAM Scheme
  12. An Energy-efficient and High-precision Approximate MAC with Distributed Arithmetic Circuits
  13. Data Stream Oriented Fine-grained Sparse CNN Accelerator with Efficient Unstructured Pruning Strategy
  14. DNN Intellectual Property Protection
  15. Approximate Computing: From Circuits to Applications
  16. Hybrid Low Radix Encoding-Based Approximate Booth Multipliers
  17. Design, evaluation and application of approximate-truncated Booth multipliers
  18. High Performance Modular Multiplication for SIDH
  19. Security Analysis of Hardware Trojans on Approximate Circuits
  20. AxSA: On the Design of High-Performance and Power-Efficient Approximate Systolic Arrays for Matrix Multiplication
  21. Dither-based calibration of bit weights in pipelined-SAR ADCs with fast convergence speed using partially split structure
  22. Embedding Backdoors as the Facial Features
  23. Lightweight Modeling Attack-Resistant Multiplexer-Based Multi-PUF (MMPUF) Design on FPGA
  24. An Efficient and Parallel R-LWE Cryptoprocessor
  25. Guest Editorial: Introduction to the Special Section on Cyber Security Threats and Defense Advance
  26. A Retrospective and Prospective View of Approximate Computing [Point of View}
  27. Attenuation-factor error shaping technique for split CDAC in SAR ADCs
  28. DPAEG: A Dependency Parse-Based Adversarial Examples Generation Method for Intelligent Q&A Robots
  29. Background Calibration of Bit Weights in Pipelined-SAR ADCs Using Paired Comparators
  30. Machine Learning Security: Threats, Countermeasures, and Evaluations
  31. Profile-Based Output Error Compensation for Approximate Arithmetic Circuits
  32. Resource-Shared Crypto-Coprocessor of AES Enc/Dec With SHA-3
  33. High Performance CNN Accelerators Based on Hardware and Algorithm Co-Optimization
  34. Security in Approximate Computing and Approximate Computing for Security: Challenges and Opportunities
  35. Lightweight Configurable Ring Oscillator PUF Based on RRAM/CMOS Hybrid Circuits
  36. Optimized Modular Multiplication for Supersingular Isogeny Diffie-Hellman
  37. New Majority Gate-Based Parallel BCD Adder Designs for Quantum-Dot Cellular Automata
  38. Design and Analysis of Approximate Redundant Binary Multipliers
  39. XOR-Based Low-Cost Reconfigurable PUFs for IoT Security
  40. Building an Accurate Hardware Trojan Detection Technique from Inaccurate Simulation Models and Unlabeled ICs
  41. A Theoretical Model to Link Uniqueness and Min-Entropy for PUF Evaluations
  42. Defeating Untrustworthy Testing Parties: A Novel Hybrid Clustering Ensemble Based Golden Models-Free Hardware Trojan Detection Method
  43. Optimized Schoolbook Polynomial Multiplication for Compact Lattice-Based Cryptography on FPGA
  44. Approximate Designs for Fast Fourier Transform (FFT) With Application to Speech Recognition
  45. Design and Evaluation of Approximate Logarithmic Multipliers for Low Power Error-Tolerant Applications
  46. Design, Evaluation and Application of Approximate High-Radix Dividers
  47. Design of Dynamic Range Approximate Logarithmic Multipliers
  48. Data Compression Device Based on Modified LZ4 Algorithm
  49. Ultra-Lightweight and Reconfigurable Tristate Inverter Based Physical Unclonable Function Design
  50. High Performance Parallel Decimal Multipliers Using Hybrid BCD Codes
  51. Designs of Approximate Floating-Point Multipliers with Variable Accuracy for Error-Tolerant Applications
  52. Design of Approximate Radix-4 Booth Multipliers for Error-Tolerant Computing
  53. Algorithm and Design of a Fully Parallel Approximate Coordinate Rotation Digital Computer (CORDIC)
  54. Design of Approximate Logarithmic Multipliers
  55. Design of Approximate High-Radix Dividers by Inexact Binary Signed-Digit Addition
  56. Design of High-Speed Wide-Word Hybrid Parallel-Prefix/Carry-Select and Skip Adders
  57. Design and Analysis of Inexact Floating-Point Adders
  58. Design of Approximate Unsigned Integer Non-restoring Divider for Inexact Computing