All Stories

  1. SSAT: Active Authorization Control and User’s Fingerprint Tracking Framework for DNN IP Protection
  2. An Imperceptible and Owner-unique Watermarking Method for Graph Neural Networks
  3. Tracking the Leaker: An Encodable Watermarking Method for Dataset Intellectual Property Protection
  4. VLCP: A High-Performance FPGA-based CNN Accelerator with Vector-level Cluster Pruning
  5. An RRAM-based PUF with Adjustable Programmable Voltage and Multi-Mode Operation
  6. An Efficient Ring Oscillator PUF Using Programmable Delay Units on FPGA
  7. Low-cost stochastic number generator based on MRAM for stochastic computing
  8. HEADiv: A High-accuracy Energy-efficient Approximate Divider with Error Compensation
  9. High-performance STT-MRAM Logic-in-Memory Scheme Utilizing Data Read Features
  10. Capacity-oriented High-performance NV-TCAM Leveraging Hybrid MRAM Scheme
  11. An Energy-efficient and High-precision Approximate MAC with Distributed Arithmetic Circuits
  12. Data Stream Oriented Fine-grained Sparse CNN Accelerator with Efficient Unstructured Pruning Strategy
  13. DNN Intellectual Property Protection
  14. Approximate Computing: From Circuits to Applications
  15. Hybrid Low Radix Encoding-Based Approximate Booth Multipliers
  16. Design, evaluation and application of approximate-truncated Booth multipliers
  17. High Performance Modular Multiplication for SIDH
  18. Security Analysis of Hardware Trojans on Approximate Circuits
  19. AxSA: On the Design of High-Performance and Power-Efficient Approximate Systolic Arrays for Matrix Multiplication
  20. Dither-based calibration of bit weights in pipelined-SAR ADCs with fast convergence speed using partially split structure
  21. Embedding Backdoors as the Facial Features
  22. Lightweight Modeling Attack-Resistant Multiplexer-Based Multi-PUF (MMPUF) Design on FPGA
  23. An Efficient and Parallel R-LWE Cryptoprocessor
  24. Guest Editorial: Introduction to the Special Section on Cyber Security Threats and Defense Advance
  25. A Retrospective and Prospective View of Approximate Computing [Point of View}
  26. Attenuation-factor error shaping technique for split CDAC in SAR ADCs
  27. DPAEG: A Dependency Parse-Based Adversarial Examples Generation Method for Intelligent Q&A Robots
  28. Background Calibration of Bit Weights in Pipelined-SAR ADCs Using Paired Comparators
  29. Machine Learning Security: Threats, Countermeasures, and Evaluations
  30. Profile-Based Output Error Compensation for Approximate Arithmetic Circuits
  31. Resource-Shared Crypto-Coprocessor of AES Enc/Dec With SHA-3
  32. High Performance CNN Accelerators Based on Hardware and Algorithm Co-Optimization
  33. Security in Approximate Computing and Approximate Computing for Security: Challenges and Opportunities
  34. Lightweight Configurable Ring Oscillator PUF Based on RRAM/CMOS Hybrid Circuits
  35. Optimized Modular Multiplication for Supersingular Isogeny Diffie-Hellman
  36. New Majority Gate-Based Parallel BCD Adder Designs for Quantum-Dot Cellular Automata
  37. Design and Analysis of Approximate Redundant Binary Multipliers
  38. XOR-Based Low-Cost Reconfigurable PUFs for IoT Security
  39. Building an Accurate Hardware Trojan Detection Technique from Inaccurate Simulation Models and Unlabeled ICs
  40. A Theoretical Model to Link Uniqueness and Min-Entropy for PUF Evaluations
  41. Defeating Untrustworthy Testing Parties: A Novel Hybrid Clustering Ensemble Based Golden Models-Free Hardware Trojan Detection Method
  42. Optimized Schoolbook Polynomial Multiplication for Compact Lattice-Based Cryptography on FPGA
  43. Approximate Designs for Fast Fourier Transform (FFT) With Application to Speech Recognition
  44. Design and Evaluation of Approximate Logarithmic Multipliers for Low Power Error-Tolerant Applications
  45. Design, Evaluation and Application of Approximate High-Radix Dividers
  46. Design of Dynamic Range Approximate Logarithmic Multipliers
  47. Data Compression Device Based on Modified LZ4 Algorithm
  48. Ultra-Lightweight and Reconfigurable Tristate Inverter Based Physical Unclonable Function Design
  49. High Performance Parallel Decimal Multipliers Using Hybrid BCD Codes
  50. Designs of Approximate Floating-Point Multipliers with Variable Accuracy for Error-Tolerant Applications
  51. Design of Approximate Radix-4 Booth Multipliers for Error-Tolerant Computing
  52. Algorithm and Design of a Fully Parallel Approximate Coordinate Rotation Digital Computer (CORDIC)
  53. Design of Approximate Logarithmic Multipliers
  54. Design of Approximate High-Radix Dividers by Inexact Binary Signed-Digit Addition
  55. Design of High-Speed Wide-Word Hybrid Parallel-Prefix/Carry-Select and Skip Adders
  56. Design and Analysis of Inexact Floating-Point Adders
  57. Design of Approximate Unsigned Integer Non-restoring Divider for Inexact Computing