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  1. AxOMaP : Designing FPGA-based A ppro x imate Arithmetic O perators using Ma thematical P ...

    Article • ACM Transactions on Reconfigurable Technology and Systems, April 2024, ACM (Association for Computing Machinery)

    Dr. Siva Satyendra Sahoo

  2. Exploring ML for designing low-overhead arithmetic operator circuits.

    Article • ACM Transactions on Embedded Computing Systems, September 2023, ACM (Association for Computing Machinery)

    Dr. Siva Satyendra Sahoo

  3. CLAppED: A Design Framework for Implementing Cross-Layer Approximation in FPGA-based Embedded Systems

    Article • December 2021, Institute of Electrical & Electronics Engineers (IEEE)

    Dr. Siva Satyendra Sahoo

  4. CLEO-CoDe: Exploiting Constrained Decoding for Cross-Layer Energy Optimization in Heterogeneous Embedded Systems

    Article • October 2021, Institute of Electrical & Electronics Engineers (IEEE)

    Dr. Siva Satyendra Sahoo

  5. Using Monte Carlo Tree Search for EDA – A Case-study with Designing Cross-layer Reliability for Heterogeneous Embedded Systems

    Article • October 2021, Institute of Electrical & Electronics Engineers (IEEE)

    Dr. Siva Satyendra Sahoo

  6. Emergent design challenges for embedded systems and paths forward

    Article • September 2021, ACM (Association for Computing Machinery)

    Dr. Siva Satyendra Sahoo

  7. ReLAccS: A Multilevel Approach to Accelerator Design for Reinforcement Learning on FPGA-Based Systems

    Article • IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, September 2021, Institute of Electrical & Electronics Engineers (IEEE)

    Dr. Siva Satyendra Sahoo

  8. MemOReL

    Article • June 2021, ACM (Association for Computing Machinery)

    Dr. Siva Satyendra Sahoo

  9. Area-Optimized Accurate and Approximate Softcore Signed Multiplier Architectures

    Article • IEEE Transactions on Computers, March 2021, Institute of Electrical & Electronics Engineers (IEEE)

    Dr. Siva Satyendra Sahoo

  10. Improving the Timing Behaviour of Mixed-Criticality Systems Using Chebyshev's Theorem

    Article • February 2021, Institute of Electrical & Electronics Engineers (IEEE)

    Dr. Siva Satyendra Sahoo

  11. Reliability-Aware Resource Management in Multi-/Many-Core Systems: A Perspective Paper

    Article • Journal of Low Power Electronics and Applications, January 2021, MDPI AG

    Dr. Siva Satyendra Sahoo

  12. BOT-MICS: Bounding Time Using Analytics in Mixed-Criticality Systems

    Article • IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, January 2021, Institute of Electrical & Electronics Engineers (IEEE)

    Dr. Siva Satyendra Sahoo

  13. ExPAN(N)D: Exploring Posits for Efficient Artificial Neural Network Design in FPGA-Based Systems

    Article • IEEE Access, January 2021, Institute of Electrical & Electronics Engineers (IEEE)

    Dr. Siva Satyendra Sahoo

  14. Markov Chain-based Modeling and Analysis of Checkpointing with Rollback Recovery for Efficient DSE in Soft Real-time Systems

    Article • October 2020, Institute of Electrical & Electronics Engineers (IEEE)

    Dr. Siva Satyendra Sahoo

  15. CL(R)Early: An Early-stage DSE Methodology for Cross-Layer Reliability-aware Heterogeneous Embedded Systems

    Article • July 2020, Institute of Electrical & Electronics Engineers (IEEE)

    Dr. Siva Satyendra Sahoo

  16. DiSCERN: Distilling Standard-Cells for Emerging Reconfigurable Nanotechnologies

    Article • March 2020, Institute of Electrical & Electronics Engineers (IEEE)

    Dr. Siva Satyendra Sahoo

  17. Multi-objective design space exploration for system partitioning of FPGA-based Dynamic Partially Reconfigurable Systems

    Article • Integration, July 2019, Elsevier

    Dr. Siva Satyendra Sahoo

  18. A Hybrid Agent-based Design Methodology for Dynamic Cross-layer Reliability in Heterogeneous Embedded Systems

    Article • June 2019, ACM (Association for Computing Machinery)

    Dr. Siva Satyendra Sahoo

  19. QoS-Aware Cross-Layer Reliability-Integrated FPGA-Based Dynamic Partially Reconfigurable System Partitioning

    Article • December 2018, Institute of Electrical & Electronics Engineers (IEEE)

    Dr. Siva Satyendra Sahoo

  20. Lifetime-aware design methodology for dynamic partially reconfigurable systems

    Article • January 2018, Institute of Electrical & Electronics Engineers (IEEE)

    Dr. Siva Satyendra Sahoo

  21. CLRFrame: An Analysis Framework for Designing Cross-Layer Reliability in Embedded Systems

    Article • January 2018, Institute of Electrical & Electronics Engineers (IEEE)

    Dr. Siva Satyendra Sahoo

  22. Cross-layer fault-tolerant design of real-time systems

    Article • September 2016, Institute of Electrical & Electronics Engineers (IEEE)

    Dr. Siva Satyendra Sahoo

  23. Design and Evaluation of Reliability-oriented Task Re-Mapping in MPSoCs using Time-Series Analysis of Intermittent Faults

    Article • January 2016, Research Publishing Services

    Dr. Siva Satyendra Sahoo