All Stories

  1. A low latency and low power indirect topology for on-chip communication

    Article • PLoS ONE, October 2019, PLOS

    Dr. sarzamin khan

  2. An Enhanced Simulation Framework for the Performance Evaluation of On-Chip Network Designs

    Article • November 2018, Institute of Electrical & Electronics Engineers (IEEE)

    Dr. sarzamin khan

  3. An optimized hybrid algorithm in term of energy and performance for mapping real time workloads on 2d based on-chip networks

    Article • Applied Intelligence, July 2018, Springer Science + Business Media

    Dr. sarzamin khan

  4. Network on chip simulators

    Article • IET Computers & Digital Techniques, January 2018, the Institution of Engineering and Technology (the IET)

    Dr. sarzamin khan

  5. An Efficient Algorithm for Mapping Real Time Embedded Applications on NoC Architecture

    Article • IEEE Access, January 2018, Institute of Electrical & Electronics Engineers (IEEE)

    Dr. sarzamin khan

  6. An Efficient and Scalable Cross-By-Pass-Mesh Architecture for On-Chip Communication

    Article • IET Computers & Digital Techniques, July 2017, the Institution of Engineering and Technology (the IET)

    Sheraz Anjum, Dr Frank Sill Torres, Dr. sarzamin khan, Usman Gulzari

  7. Bandwidth-Constrained Multi-Objective Segmented Brute-Force Algorithm for Efficient Mapping of Embedded Applications on NoC Architecture

    Article • IEEE Access, January 2017, Institute of Electrical & Electronics Engineers (IEEE)

    Dr. sarzamin khan