All Stories

  1. (Invited) New Layout Styles to Boost the Electrical, Energy, and Frequency Response Performances of Analog MOSFETs, Considering a Wide Range of High Temperatures
  2. Impact in the Parallel Processing of IHM-Plasma Using the Earliest-Deadline-First Algorithm for the Task-Scheduler Realized by Hardware
  3. (Invited) New Layout Styles to Boost the Electrical, Energy, and Frequency Response Performances of Analog MOSFETs, Considering a Wide Range of High Temperatures
  4. Differentiated Layout Styles for MOSFETs
  5. Introduction
  6. The MOSFET
  7. Basic Concepts of the Semiconductor Physics
  8. The Electrical Characteristics of the Semiconductor at High Temperatures
  9. The First Generation of the Unconventional Layout Styles for MOSFETs
  10. The Second Generation of the Unconventional Layout Styles (HYBRID) for MOSFETs
  11. The Ionizing Radiations Effects in Electrical Parameters and Figures of Merit of Mosfets
  12. The High Temperatures’ Effects on the Conventional (Rectangular) and Non-conventional Layout Styles of the First and Second Generations for MOSFETs
  13. Using iMTGSPICE to Optimize Cascaded Miller OTAs and Boost Electrical Performance, Robustness and Reduce Die Area
  14. Customized Imperialist Competitive Algorithm Methodology to Optimize Robust Miller CMOS OTAs
  15. Second Generation of Layout Styles to Further Boosting the Electrical Performance and Reducing the Die Area of Analog MOSFETs
  16. Impact of Temperature Effects in the Zero Temperature Coefficient of the Ellipsoidal MOSFET
  17. Total Ionizing Dose (X-Ray) Effects on the Mismaching of the Analog MOSFETs layouted with Different Layout Sytles
  18. Impact of using Octogonal Layout Style in Planar Power MOSFETs
  19. New Hybrid Generation of Layout Styles to Boost the Electrical, Energy, and Frequency Response Performances of Analog MOSFETs
  20. Optimizing a Robust Miller OTA Implemented with Diamond Layout Style for MOSFETs By Using iMTGSPICE
  21. Comparative Study Between Conventional and Wave Planar Power Mosfets
  22. The Second Generation of the Layout Styles for MOSFETs to Further Boosting the Electrical Performance of Analog MOSFETs and CMOS ICs
  23. LCE and PAMDLE Effects From Diamond Layout for MOSFETs at High-Temperature Ranges
  24. The Impact of LCE and PAMDLE Regarding Different CMOS ICs Nodes and High Temperatures
  25. Optimization of a low noise amplifier with two technology nodes using an interactive evolutionary approach
  26. Boosting the MOSFETs Matching by Using Diamond Layout Style
  27. Using the Octagonal Layout Style for MOSFETs to Boost the Device Matching in Ionizing Radiation Environments
  28. Methodology to optimize and reduce the total gate area of robust operational transconductance amplifiers by using diamond layout style for MOSFETs
  29. Zero Temperature Coefficient behavior for Ellipsoidal MOSFET
  30. Using the Hexagonal Layout Style for MOSFETs to Boost the Device Matching in Ionizing Radiation Environments
  31. Electrical Behavior of Effects LCE and PAMDLE of the Ellipsoidal MOSFETs in a Huge Range of High Temperatures
  32. Electrical Behavior of Effects LCE and PAMDLE of the Ellipsoidal MOSFETs in a Huge Range of High Temperatures
  33. A customized genetic algorithm with in-loop robustness analyses to boost the optimization process of analog CMOS ICs
  34. An innovative strategy to reduce die area of robust OTA by using iMTGSPICE and diamond layout style for MOSFETs
  35. Interactive evolutionary approach to reduce the optimization cycle time of a low noise amplifier
  36. Digital Performance of OCTO Layout Style on SOI MOSFET at High Temperature Environment
  37. Boosting the Performance of MOSFET Operating Under a Huge Range of High Temperature by Using the Octagonal Layout Style
  38. Boosting the Ionizing Radiation Tolerance in the Mosfets Matching by Using Diamond Layout Style
  39. A Novel Processor Architecture With a Hardware Microkernel to Improve the Performance of Task-Based Systems
  40. Erratum: Impact of designer knowledge in the interactive evolutionary optimisation of analogue CMOS ICs by using iMTGSPICE
  41. Minimizing the TID effects due to gamma rays by using diamond layout for MOSFETs
  42. 8051 Microcontrollers
  43. Impact of designer knowledge in the interactive evolutionary optimization of analog CMOS ICs by using iMTGSPICE
  44. Overview About Radiation–Matter Interaction Mechanisms and Mitigation Techniques
  45. Automatic Optimization of Robust Analog CMOS ICs: An Interactive Genetic Algorithm Driven by Human Knowledge
  46. Using Statistical Student’s t-Test to Qualify the Electrical Performance of the Diamond MOSFETs
  47. Impact of the Octagonal Layout Style for MOSFETs using 180nm Bulk CMOS ICs Technology Node
  48. Improvement Of The Harmonic Distortion By Using Diamond Mosfet
  49. 8051 Core Microcontrollers
  50. Flowchart and Assembly Programming
  51. Fundamental Concepts of Computer Systems
  52. Basic 8051 Core Microcontroller Interruptions
  53. Input/Output Ports of 8051 Core Microcontrollers
  54. Timers/Counters of the 8051 Core Microcontroller
  55. Subroutine and Structuring of the Assembly Programming Language
  56. 8051 Microcontroller Instruction Set of the 8051 Core
  57. The Serial Communication Interface of the 8051 Core Microcontroller
  58. Experimental Study for Mosfet with Ellipsoidal Layout
  59. Using Ellipsoidal Layout Style to Boost the Electrical Performance of the MOSFETs Regarding the 180 nm CMOS ICs Manufacturing Process
  60. Using the Octagonal Layout Style to Implement the Pass MOSFET to Improve the Electrical Performance of the CL–LDO Voltage Regulator
  61. Gaussian Fitness Functions for Optimizing Analog CMOS Integrated Circuits
  62. Improving MOSFETs’ TID Tolerance Through Diamond Layout Style
  63. Comparative experimental study of the improved MOSFETs matching by using the hexagonal layout style
  64. VI-Based Measurement System Focusing on Space Applications
  65. Boosting the SOI MOSFET Electrical Performance by Using the Octagonal Layout Style in High Temperature Environment
  66. Study of proton radiation effects among diamond and rectangular gate MOSFET layouts
  67. Boosting the MOSFETs matching by using diamond layout style
  68. Zero cost layout technique for MOSFETs
  69. From architecture to manufacturing: an accurate framework for optimal operational transconductance amplifier design
  70. From architecture to manufacturing: an accurate framework for optimal operational transconductance amplifier design
  71. Layout Techniques for MOSFETS
  72. Introduction
  73. Conclusions and Comments
  74. Ellipsoidal Layout Style for MOSFET
  75. Diamond MOSFET (Hexagonal Gate Geometry)
  76. Electrical behavior of the Diamond layout style for MOSFETs in X-rays ionizing radiation environments
  77. Impact of Using the Octagonal Layout for SOI MOSFETs in a High-Temperature Environment
  78. From architecture to manufacturing: An accurate framework for optimal OTA design
  79. Boosting the total ionizing dose tolerance of digital switches by using OCTO SOI MOSFET
  80. Boosting the electrical performance of MOSFET switches by applying Ellipsoidal layout style
  81. An Innovative Ellipsoidal Layout Style to Further Boost the Electrical Performance of MOSFETs
  82. Using the Wave Layout Style to Boost the Digital ICs Electrical Performance in the Radioactive Environment
  83. Diamond layout style impact on SOI MOSFET in high temperature environment
  84. A New Test Environment Approach to SEE Detection in MOSFETs
  85. Non-standard layout styles for MOSFETs
  86. Improving MOSFETs radiation robustness by using the wave layout to boost analog ICs applications
  87. Boosting the radiation hardness and higher reestablishing pre-rad conditions by using OCTO layout style for MOSFETs
  88. Boosting the performance of the planar power MOSFET By using Diamond layout style
  89. HEXAGONAL GATE SHAPE (DIAMOND) FOR MOSFETS
  90. Innovative Layout Styles to Boost the Mosfet Electrical Performance
  91. Experimental comparative study between the diamond MOSFET and its conventional counterpart in high temperatures environment
  92. Analysis of a New Evolutionary System Elitism for Improving the Optimization of a CMOS OTA
  93. Total ionizing dose effects on the digital performance of irradiated OCTO and conventional fully depleted SOI MOSFET
  94. Total ionizing dose radiation effects between the Wave layout style and its conventional counterpart focusing on the digital IC applications
  95. Improving the X-ray radiation tolerance of the analog ICs by using OCTO layout style
  96. OCTO FinFET
  97. Comparative Experimental Study between Tensile and Compressive Uniaxially Stressed nMuGFETs under X-ray Radiation Focusing on Analog Behavior
  98. Projeto de um OTA CMOS por meio de um sistema evolucionário integrado ao SPICE
  99. Using OCTO SOI nMOSFET to Handle High Current for Automotive Modules
  100. Using Numerical Simulations to Study and Design Semiconductors Devices in Micro and Nanoelectronics
  101. Experimental Comparative Study Between the Wave Layout Style and its Conventional Counterpart for Implementation of Analog Integrated Circuits
  102. Applying the Diamond Layout Style for FinFET
  103. Experimental Study of the OCTO SOI nMOSFET and Its Application in Analog Integrated Circuits
  104. Experimental Validation of the Drain Current Analytical Model of the Fully Depleted Diamond SOI nMOSFETs by Using Paired T-test Statistical Evaluation
  105. Modeling and Characterization of Overlapping Circular-Gate mosfet and Its Application to Power Devices
  106. AGSPICE: A new analog ICs design tool based on evolutionary electronics used for extracting additional design recommendations
  107. Comparative study of the proton beam effects between the conventional and Circular-Gate MOSFETs
  108. Performance of electronic devices submitted to X-rays and high energy proton beams
  109. FISH SOI MOSFET: An Evolution of the Diamond SOI Transistor for Digital ICs Applications
  110. X-ray Radiation Effects in Circular-Gate Transistors
  111. FISH SOI MOSFET: Modeling, Characterization and Its Application to Improve the Performance of Analog ICs
  112. FISH SOI MOSFET: An Evolution of the Diamond SOI Transistor for Digital ICs Applications
  113. X-ray Radiation Effects in Circular-Gate Transistors
  114. Diamond MOSFET: An innovative layout to improve performance of ICs
  115. Comparative Experimental Study between Diamond and Conventional MOSFET
  116. Comparative Experimental Study between Diamond and Conventional MOSFET
  117. Drain Leakage Current Evaluation in the Diamond SOI nMOSFET at High Temperatures
  118. A Novel Overlapping Circular-Gate Transistor and its Application to Power MOSFETs
  119. The Wave SOI MOSFET: A New Accuracy Transistor Layout to Improve Drain Current and Reduce Die Area for Current Drivers Applications
  120. Using Cynthia SOI MOSFET to Improve Voltage Gain of Analog Integrated Circuits
  121. Early Voltage Behavior in Circular Gate SOI nMOSFET Using 0.13 μm Partially-Depleted SOI CMOS Technology
  122. Comparison Between Harmonic Distortion in Circular Gate and Conventional SOI nMOSFET Using 0.13 [micro sign]m Partially-Depleted SOI CMOS Technology
  123. Implementation of High Performance Operational Transconductance Amplifiers using Graded-Channel SOI nMOSFETs
  124. Gain improvement in operational transconductance amplifiers using Graded-Channel SOI nMOSFETS
  125. 8051 microcontroller structure
  126. 8051 instruction set
  127. Design of operational transconductance amplifiers with improved gain by using graded-channel SOI nMOSFETs