All Stories

  1. Performance Analysis of CNN Inference/Training with Convolution and Non-Convolution Operations on ASIC Accelerators
  2. IR-Aware ECO Timing Optimization Using Reinforcement Learning
  3. An Open-Source ML-Based Full-Stack Optimization Framework for Machine Learning Accelerators
  4. A Machine Learning Approach to Improving Timing Consistency between Global Route and Detailed Route
  5. On Endurance of Processing in (Nonvolatile) Memory
  6. The ALIGN Automated Analog Layout Engine
  7. Recent Progress in the Analysis of Electromigration and Stress Migration in Large Multisegment Interconnects
  8. A Generalized Methodology for Well Island Generation and Well-Tap Insertion in Analog/Mixed-Signal Layouts
  9. Performance-driven Wire Sizing for Analog Integrated Circuits
  10. Encoder-Decoder Networks for Analyzing Thermal and Power Delivery Networks
  11. A Novel Semi-Analytical Approach for Fast Electromigration Stress Analysis in Multi-Segment Interconnects
  12. Energy-efficient and Reliable Inference in Nonvolatile Memory under Extreme Operating Conditions
  13. Physically Accurate Learning-based Performance Prediction of Hardware-accelerated ML Algorithms
  14. From Global Route to Detailed Route: ML for Fast and Accurate Wire Parasitics and Timing Prediction
  15. Analog/Mixed-Signal Layout Optimization using Optimal Well Taps
  16. Spiking Neural Networks in Spintronic Computational RAM
  17. CAMeleon
  18. Machine Learning Techniques in Analog Layout Automation
  19. A customized graph neural network model for guiding analog IC placement
  20. PIMBALL
  21. Stress-Induced Performance Shifts in 3D DRAMs
  22. ALIGN
  23. True In-memory Computing with the CRAM
  24. Optimal design of JPEG hardware under the approximate computing paradigm
  25. Joint precision optimization and high level synthesis for approximate computing