All Stories

  1. Learning to Compare Hardware Designs for High-Level Synthesis
  2. Cross-Modality Program Representation Learning for Electronic Design Automation with High-Level Synthesis
  3. PASTA: Programming and Automation Support for Scalable Task-Parallel HLS Programs on Modern Multi-Die FPGAs
  4. CHARM 2.0: Composing Heterogeneous Accelerators for Deep Learning on Versal ACAP Architecture
  5. Q-Pilot: Field Programmable Qubit Array Compilation with Flying Ancillas
  6. SpectraFlux: Harnessing the Flow of Multi-FPGA in Mass Spectrometry Clustering
  7. TAPA-CS: Enabling Scalable Accelerator Design on Distributed HBM-FPGAs
  8. Automatic Hardware Pragma Insertion in High-Level Synthesis: A Non-Linear Programming Approach
  9. FPGA-based Accelerator for Sparse Triangular Solver
  10. Scheduling and Physical Design
  11. TAPA: A Scalable Task-Parallel Dataflow Programming Framework for Modern FPGAs with Co-Optimization of HLS and Physical Design
  12. Caffeine: Towards Uniformed Representation and Acceleration for Deep Convolutional Neural Networks
  13. NeSSA: Near-Storage Data Selection for Accelerated Machine Learning Training
  14. RapidStream 2.0: Automated Parallel Implementation of Latency Insensitive FPGA Designs Through Partial Reconfiguration
  15. FPGA Acceleration of Probabilistic Sentential Decision Diagrams with High-level Synthesis
  16. FlexCNN: An End-to-end Framework for Composing CNN Accelerators on FPGA
  17. HMLib: Efficient Data Transfer for HLS Using Host Memory
  18. Callipepla: Stream Centric Instruction Set and Mixed Precision for Accelerating Conjugate Gradient Solver
  19. CHARM: C omposing H eterogeneous A ccele R ators for M atrix Multiply on Versal ACAP Architecture
  20. FPGA HLS Today: Successes, Challenges, and Opportunities
  21. Qubit Mapping for Reconfigurable Atom Arrays
  22. OverGen: Improving FPGA Usability through Domain-specific Overlay Generation
  23. Energy-Efficient LSTM Inference Accelerator for Real-Time Causal Prediction
  24. N-DISE
  25. AutoDSE: Enabling Software Programmers to Design Efficient FPGA Accelerators
  26. Serpens
  27. Automated accelerator optimization aided by graph neural networks
  28. Improving GNN-based accelerator design automation with meta learning
  29. Automated Accelerator Optimization Aided by Graph Neural Networks
  30. SPA-GCN: Efficient and Flexible GCN Accelerator with Application for Graph Similarity Computation
  31. Sextans: A Streaming Accelerator for General-Purpose Sparse-Matrix Dense-Matrix Multiplication
  32. Accelerating SSSP for Power-Law Graphs
  33. RapidStream
  34. TENET: A Framework for Modeling Tensor Dataflow Based on Relation-centric Notation
  35. AutoBridge
  36. Extending High-Level Synthesis for Task-Parallel Programs
  37. HBM Connect: High-Performance HLS Interconnect for FPGA HBM
  38. MOCHA
  39. AutoDSE: Enabling Software Programmers Design Efficient FPGA Accelerators
  40. AutoSA
  41. BLINK
  42. HeteroRefactor
  43. Bonsai: High-Performance Adaptive Merge Tree Sorting
  44. Overcoming Data Transfer Bottlenecks in FPGA-based DNN Accelerators via Layer Conscious Memory Management
  45. Dataflow Systolic Array Implementations of Matrix Decomposition Using High Level Synthesis
  46. LANMC
  47. HeteroCL
  48. Overcoming Data Transfer Bottlenecks in DNN Accelerators via Layer-Conscious Memory Managment
  49. CPU-FPGA Co-Optimization for Big Data Applications
  50. Bandwidth Optimization Through On-Chip Memory Restructuring for HLS
  51. Energy-Efficient CNN Implementation on a Deeply Pipelined FPGA Cluster
  52. Invited - Heterogeneous datacenters
  53. Energy Efficiency of Full Pipelining: A Case Study for Matrix Multiplication
  54. Caffeine
  55. ARAPrototyper
  56. InterFS
  57. CMOST
  58. On-chip interconnection network for accelerator-rich architectures
  59. A Fully Pipelined and Dynamically Composable Architecture of CGRA
  60. Automatic memory partitioning and scheduling for throughput and power optimization