All Stories

  1. Mitigating Cache Contention-Based Attacks by Logical Associativity
  2. Using Formal Methods to Evaluate Hardware Reliability in the Presence of Soft Errors
  3. A Survey on the Susceptibility of PUFs to Invasive, Semi-Invasive and Noninvasive Attacks: Challenges and Opportunities for Future Directions
  4. Learning-based BTI stress estimation and mitigation in multi-core processor systems
  5. Anomaly Detection in an Embedded System
  6. A Cost-Efficient Aging Sensor Based on Multiple Paths Delay Fault Monitoring
  7. Ageing Mitigation Techniques for SRAM Memories
  8. Ageing-Aware Logic Synthesis
  9. Aging Mitigation Techniques for Microprocessors Using Anti-aging Software
  10. A reliable PUF in a dual function SRAM
  11. Two-Stage Architectures for Resilient Lightweight PUFs
  12. Using Hardware Performance Counters to Detect Control Hijacking Attacks
  13. VLSI Implementation of a Fully-Pipelined K-Best MIMO Detector with Successive Interference Cancellation
  14. Editorial TVLSI Positioning—Continuing and Accelerating an Upward Trajectory
  15. Fault Analysis in Analog Circuits Through Language Manipulation and Abstraction
  16. A Power Efficient Crossbar Arbitration in Multi-NoC for Multicast and Broadcast Traffic
  17. Lifetime Reliability-Aware Digital Synthesis
  18. Cell Flipping with Distributed Refresh for Cache Ageing Minimization
  19. A Machine Learning Attacks Resistant Two Stage Physical Unclonable Functions Design
  20. A Reliable PUF in a Dual Function SRAM
  21. Hardware Implementation of a Low-Power K-Best MIMO Detector Based on a Hybrid Merge Network
  22. Multi-Path Aging Sensor for Cost-Efficient Delay Fault Prediction
  23. Cost-efficient design for modeling attacks resistant PUFs
  24. Early detection of system-level anomalous behaviour using hardware performance counters
  25. BTI mitigation by anti-ageing software patterns
  26. Fault analysis in analog circuits through language manipulation and abstraction
  27. Hardware performance counters for system reliability monitoring
  28. Lightweight obfuscation techniques for modeling attacks resistant PUFs
  29. An ageing-aware digital synthesis approach
  30. A cost-efficient delay-fault monitor
  31. Overview of PUF-based hardware security solutions for the internet of things
  32. Sigma-n LBDR: Generic Congestion Handling Routing Implementation for 2D mesh NoC
  33. Guest Editorial
  34. Using I<inf>ddt</inf> current degradation to monitor ageing in CMOS circuits
  35. NBTI aging evaluation of PUF-based differential architectures
  36. High accuracy implementation of Adaptive Exponential integrated and fire neuron model
  37. The European Masters in Embedded Computing Systems (EMECS)
  38. The influence of hysteresis voltage on single event transients in a 65nm CMOS high speed comparator
  39. A Low-Cost, Radiation-Hardened Method for Pipeline Protection in Microprocessors
  40. SystemC-AMS Simulation of Conservative Behavioral Descriptions
  41. IEEE Access Special Section Editorial: Security and Reliability Aware System Design for Mobile Computing Devices
  42. Resilient routing implementation in 2D mesh NoC
  43. A Survey of VLSI Implementations of Tree Search Algorithms for MIMO Detection
  44. Improved adaptive routing for networks‐on‐chip
  45. VLSI implementation of a scalable K-best MIMO detector
  46. An application-specific NBTI ageing analysis method
  47. A framework for thermal aware reliability estimation in 2D NoC
  48. Network-on-chip: Current issues and challenges
  49. Reliability analysis of comparators
  50. TCO-PUF: A subthreshold physical unclonable function
  51. σLBDR: Congestion-aware logic based distributed routing for 2D NoC
  52. Parallel Sparse Matrix Solution for Circuit Simulation on FPGAs
  53. Resistive Open Faults Detectability Analysis and Implications for Testing Low Power Nanometric ICs
  54. Conservative behavioural modelling in systemc-AMS
  55. CERI: Cost-Effective Routing Implementation Technique for Network-on-Chip
  56. Fault tolerant routing implementation mechanism for irregular 2D mesh NoCs
  57. Fault tolerant and highly adaptive routing for 2D NoCs
  58. A novel non-minimal turn model for highly adaptive routing in 2D NoCs
  59. A novel non-minimal/minimal turn model for highly adaptive routing in 2D NoCs
  60. A cost-efficient self-checking register architecture for radiation hardened designs
  61. Monte Carlo Static Timing Analysis with statistical sampling
  62. Multivoltage Aware Resistive Open Fault Model
  63. A low-cost radiation hardened flip-flop
  64. Efficient simulation and modelling of non-rectangular NoC topologies
  65. A low-cost radiation hardened flip-flop
  66. Efficient simulation and modelling of non-rectangular NoC topologies
  67. Highly adaptive and congestion-aware routing for 3D NoCs
  68. CARM: Congestion Adaptive Routing Method for On Chip Networks
  69. Evaluating system security using Transaction Level Modelling
  70. Energy-Conscious Turbo Decoder Design: A Joint Signal Processing and Transmit Energy Reduction Approach
  71. On testing of MEDA based digital microfluidics biochips
  72. An improved instruction-level energy model for RISC microprocessors
  73. Circuit simulation using state space equations
  74. Modeling the effect of process variations on the delay and power of the digital circuit using fast simulators
  75. Oscillation-based analog diagnosis using artificial neural networks based inference mechanism
  76. Circuit Transient Analysis Using State Space Equations
  77. VLSI Design and Test
  78. SETTOFF: A fault tolerant flip-flop for building Cost-efficient Reliable Systems
  79. A GPU based simulation platform for adaptive frequency hopf oscillators
  80. <title>Analysis, quantification, and mitigation of electrical variability due to layout dependent effects in SOC designs</title>
  81. A Large Scale Digital Simulation of Spiking Neural Networks (SNN) on Fast SystemC Simulator
  82. Reducing the Active Paths Interference in the Chialvo-Bak“Minibrain” Model
  83. Acceleration of packet filtering using gpgpu
  84. Parallelizing TUNAMI-N1 Using GPGPU
  85. Radiation hardening by design: A novel gate level approach
  86. Timing Vulnerability Factors of Ultra Deep-sub-micron CMOS
  87. On the VLSI Implementation of Adaptive-Frequency Hopf Oscillator
  88. Fixed-point multiplication: A probabilistic bit-pattern view
  89. Modelling circuit performance variations due to statistical variability: Monte Carlo static timing analysis
  90. Acceleration of Functional Validation Using GPGPU
  91. Modelling Smart Card Security Protocols in SystemC TLM
  92. Very large scale integration architecture for integer wavelet transform
  93. A communication infrastructure for a million processor machine
  94. Design metrics for RTL level estimation of delay variability due to intradie (random) variations
  95. Parallel sparse matrix solver for direct circuit simulations on FPGAs
  96. Multi-threaded circuit simulation using OpenMP
  97. A modified Izhikevich model for circuit implementation of spiking neural networks
  98. Optimising physical wires usage in mesh-based multi-FPGA systems using partition swapping
  99. Efficient and realistic statistical worst case delay computation using VHDL
  100. Physical realizable circuit structure for adaptive frequency Hopf oscillator
  101. Analytical transient response and propagation delay model for nanoscale CMOS inverter
  102. Variation resilient adaptive controller for subthreshold circuits
  103. New concepts of worst-case delay and yield estimation in asynchronous VLSI circuits
  104. Impact of NBTI on the performance of 35nm CMOS digital circuits
  105. Behavioural Modelling for Stability of CMOS SRAM Cells Subject to Random Discrete Doping
  106. On the probability distribution of fixed-point multiplication
  107. Closed-loop multivariable process identification in the frequency domain
  108. Symbolic noise analysis approach to computational hardware optimization
  109. Path switching: a technique to tolerate dual rail routing imbalances
  110. New concepts of worst-case delay evaluation in asynchronous VLSI SoC
  111. Delay fault modelling/simulation using VHDL-AMS in multi-Vdd systems
  112. General and Technical Program Chairs' Message
  113. Testing of Level Shifters in Multiple Voltage Designs
  114. A Symbolic Noise Analysis Approach to Word-Length Optimization in DSP Hardware
  115. A novel self-routing reconfigurable fault-tolerant cell array
  116. Multiple-Width Bus Partitioning Approach to Datapath Synthesis
  117. Using neural networks as a fault detection mechanism in MEMS devices
  118. Evaluation of Dynamic Voltage and Frequency Scaling as a Differential Power Analysis Countermeasure
  119. On the Design of Self-Checking Controllers with Datapath Interactions
  120. An Integrated High-Level On-Line Test Synthesis Tool
  121. Analogue electronic circuit diagnosis based on ANNs
  122. Reversible Logic to Cryptographic Hardware: A New Paradigm
  123. FROM SELF-TEST TO SELF-REPAIR
  124. Behavioural synthesis of an adaptive Viterbi decoder
  125. Area word-length trade off in DSP algorithm implementation and optimization
  126. Behavioral Fault Modeling and Simulation Using VHDL-AMS to Speed-Up Analog Fault Simulation
  127. Generation and Verification of Tests for Analog Circuits Subject to Process Parameter Deviations
  128. Concurrent analogue fault simulation, the equation formulation aspect
  129. Behavioural synthesis utilising dynamic memory constructs
  130. Integrating testability with design space exploration
  131. Globally convergent algorithms for dc operating point analysis of nonlinear circuits
  132. Analysis of mirror mismatch and clock-feedthrough in Bruton transformation switched current wave filters
  133. A technique for transparent fault injection and simulation in VHDL
  134. Mutual information theory for adaptive mixture models
  135. Applying mutual information theory to behavioural analogue fault modelling
  136. Synthesis system for analog circuits
  137. Simultaneous optimisation of dynamic power, area and delay in behavioural synthesis
  138. Applying a robust heteroscedastic probabilistic neural network to analog fault detection and classification
  139. In-line test of synthesised systems exploiting latency analysis
  140. Applying Mutual Information to Adaptive Mixture Models
  141. Using robust adaptive mixing for statistical fault macromodelling
  142. Simulation of losses in resonant converter circuits
  143. Bootstrap, an alternative to Monte Carlo simulation
  144. A DFT technique to increase the resolution of AC RMS power supply current monitoring of complex analogue circuits
  145. Analogue circuit synthesis from performance specifications
  146. Design for test technique for increasing the resolution of supply current monitoring in analogue circuits
  147. Issues in the design of a logic simulator: element modelling for efficiency
  148. Electrically conductive adhesives for surface mount solder replacement
  149. Macromodel of CMOS operational amplifier including supply current variation
  150. Anatomy of a simulation backplane
  151. Issues in the design of a logic simulator: an improved caching technique for event-queue management
  152. Behavioural macromodelling for analogue fault simulation
  153. Overview of SPICE-like circuit simulation algorithms
  154. Interleaving: an additional topological compaction technique for Weinberger array generation
  155. Confidence in mixed-mode circuit simulation
  156. Lee router modified for global routing
  157. Use of Existing Cell Library and Software Tools in a Silicon Compilation Environment
  158. Using Ella as a Design Tool
  159. Divided Backend Duplication Methodology for Balanced Dual Rail Routing
  160. Relaxation methods for analogue fault simulation
  161. Fault Diagnosis in Digital Part of Mixed-Mode Circuit
  162. Dynamic Voltage Scaling Aware Delay Fault Testing
  163. Word-Length Oriented Multiobjective Optimization of Area and Power Consumption in DSP Algorithm Implementation
  164. Behavioural Modelling, Simulation, Test and Diagnosis of MEMS using ANNs
  165. ANN based modeling, testing and diagnosis of MEMS
  166. Behavioural modelling of analogue faults in VHDL-AMS - a case study
  167. DC operating point analysis using evolutionary computing
  168. Integrating self testability with design space exploration by a controller based estimation technique
  169. Foundation of combined datapath and controller self-checking design
  170. The continuous-discrete interface - What does this really mean? Modelling and simulation issues
  171. Versatile high-level synthesis of self-checking datapaths using an on-line testability metric
  172. Using evolutionary and hybrid algorithms for DC operating point analysis of nonlinear circuits
  173. Behavioural modelling of operational amplifier faults using VHDL-AMS
  174. Transformation based insertion of on-line testing resources in a high-level synthesis environment
  175. Practical algorithms for fully decoupled mixed-mode simulation of electronic circuits
  176. Process variation independent built-in current sensor for analogue built-in self-test
  177. Behavioural modelling of operational amplifier faults using analogue hardware description languages
  178. Analog circuit synthesis with over-designed circuits
  179. Fast, robust DC and transient fault simulation for nonlinear analogue circuits
  180. Testing analog circuits by supply voltage variation and supply current monitoring
  181. A design for test technique to increase the resolution of analogue supply current tests
  182. Generation and verification of tests for analogue circuits subject to process parameter deviations
  183. Analogue fault modelling and simulation for supply current monitoring