All Stories

  1. Multi-Profile Encryption on FPGA for Cyber-Physical Systems
  2. Pollice verde 2.0: una nuova risorsa per un invecchiamento attivo
  3. To be assertive or not to be assertive: That is the question! Students' reactions to sexual harassment in academia
  4. A Bandwidth-Efficient Emulator of Biologically-Relevant Spiking Neural Networks on FPGA
  5. An Adaptive Cognitive Sensor Node for ECG Monitoring in the Internet of Medical Things
  6. Target-Aware Neural Architecture Search and Deployment for Keyword Spotting
  7. Runtime Adaptive IoMT Node on Multi-Core Processor Platform
  8. Author Correction: Morphological Neural Computation Restores Discrimination of Naturalistic Textures in Trans-radial Amputees
  9. Impact of pulsed-wave-Doppler velocity-envelope tracing techniques on classification of complete fetal cardiac cycles
  10. The Multi-Dataflow Composer tool: An open-source tool suite for optimized coarse-grain reconfigurable hardware accelerators and platform design
  11. A non-invasive multimodal foetal ECG–Doppler dataset for antenatal cardiology research
  12. Mutual Impact between Clock Gating and High Level Synthesis in Reconfigurable Hardware Accelerators
  13. ALOHA: A Unified Platform-Aware Evaluation Method for CNNs Execution on Heterogeneous Systems at the Edge
  14. Annotated real and synthetic datasets for non-invasive foetal electrocardiography post-processing benchmarking
  15. Systematic analysis of wavelet denoising methods for neural signal processing
  16. NeuPow
  17. Wavelet denoising as a post-processing enhancement method for non-invasive foetal electrocardiography
  18. Optimizing Temporal Convolutional Network Inference on FPGA-Based Accelerators
  19. A Novel Tool for Non-Invasive Fetal Electrocardiography Research: the NInFEA Dataset
  20. Automatic detection of complete and measurable cardiac cycles in antenatal pulsed-wave Doppler signals
  21. A Plantar Pressure Biofeedback M-Health System for Stroke Patients
  22. Morphological Neural Computation Restores Discrimination of Naturalistic Textures in Trans-radial Amputees
  23. Design and Usability Assessment of a Multi-Device SOA-Based Telecare Framework for the Elderly
  24. Feasibility Study and Porting of the Damped Least Square Algorithm on FPGA
  25. Systematic analysis of single- and multi-reference adaptive filters for non-invasive fetal electrocardiography
  26. ZyON: Enabling Spike Sorting on APSoC-Based Signal Processors for High-Density Microelectrode Arrays
  27. Dataflow-Functional High-Level Synthesis for Coarse-Grained Reconfigurable Accelerators
  28. Comparison of Single- and Multi-reference QRD-RLS adaptive filter for non-invasive fetal electrocardiography
  29. A runtime-adaptive cognitive IoT node for healthcare monitoring
  30. CERBERO: Cross-layer modEl-based fRamework for multi-oBjective dEsign of reconfigurable systems in unceRtain hybRid envirOnments
  31. NeuPow
  32. An integrated hardware/software design methodology for signal processing systems
  33. Hardware/Software Self-adaptation in CPS: The CERBERO Project Approach
  34. Reconfigurable Adaptive Multiple Transform Hardware Solutions for Versatile Video Coding
  35. Fetal Pulsed-Wave Doppler Atrioventricular Activity Detection by Envelope Extraction and Processing
  36. Six‐Month Assessment of a Hand Prosthesis with Intraneural Tactile Feedback
  37. Correction: An automated system for the objective evaluation of human gustatory sensitivity using tongue biopotential recordings
  38. Multi-Grain Reconfiguration for Advanced Adaptivity in Cyber-Physical Systems
  39. Objective Human Gustatory Sensitivity Assessment Through a Portable Electronic Device
  40. NEURA ghe
  41. Functional estimation of bony segment lengths using magneto-inertial sensing: Application to the humerus
  42. Exploiting All Programmable SoCs in Neural Signal Analysis: A Closed-Loop Control for Large-Scale CMOS Multielectrode Arrays
  43. Challenging CPS Trade-off Adaptivity with Coarse-Grained Reconfiguration
  44. Automatic Recognition of Complete Atrioventricular Activity in Fetal Pulsed-Wave Doppler Signals
  45. Impact of a TV-based Assistive Technology on Older People’s Ability to Self-manage Their Own Health
  46. Adaptive Filtering for Electromyographic Signal Processing in Scoliosis Indexes Estimation
  47. EARNEST: A 64 channel device for neural recording and sensory touch restoration in neural prosthetics
  48. A Novel Embedded System for Direct, Programmable Stimulation of the Peripheral Neural System
  49. Challenging the Best HEVC Fractional Pixel FPGA Interpolators With Reconfigurable and Multifrequency Approximate Computing
  50. An automated system for the objective evaluation of human gustatory sensitivity using tongue biopotential recordings
  51. Hardware design methodology using lightweight dataflow and its integration with low power techniques
  52. A 64-channels neural interface for biopotentials recording and PNS stimulation
  53. A Precision Pseudo Resistor Bias Scheme for the Design of Very Large Time Constant Filters
  54. Comparative evaluation of different wavelet thresholding methods for neural signal processing
  55. A closed-loop system for neural networks analysis through high density MEAs
  56. Feasibility study of real-time spiking neural network simulations on a swarm intelligence based digital architecture
  57. On-FPGA real-time processing of biological signals from high-density MEAs: a design space exploration
  58. Real-Time neural signal decoding on heterogeneous MPSocs based on VLIW ASIPs
  59. In vivo estimation of the shoulder joint center of rotation using magneto-inertial sensors: MRI-based accuracy and repeatability assessment
  60. Cross-layer design of reconfigurable cyber-physical systems
  61. An FPGA Platform for Real-Time Simulation of Spiking Neuronal Networks
  62. Estimation of the center of rotation using wearable magneto-inertial sensors
  63. A high-efficiency runtime reconfigurable IP for CNN acceleration on a mid-range all-programmable SoC
  64. Coarse grain reconfiguration: Power estimation and management flow for hybrid gated systems
  65. Demo: Reconfigurable Platform Composer Tool
  66. Low power design methodology for signal processing systems using lightweight dataflow techniques
  67. On-the-fly adaptivity for process networks over shared-memory platforms
  68. Dataflow-Based Design of Coarse-Grained Reconfigurable Platforms
  69. Real-Time Neural Signals Decoding onto Off-the-Shelf DSP Processors for Neuroprosthetic Applications
  70. Investigation on the hermeticity of an implantable package with 32 feedthroughs for neural prosthetic applications
  71. Hand tele-rehabilitation system
  72. MPSoCs for real-time neural signal decoding: A low-power ASIP-based implementation
  73. Adaptable AES implementation with power-gating support
  74. Power and clock gating modelling in coarse grained reconfigurable systems
  75. Curbing the roofline
  76. An integrated interface for peripheral neural system recording and stimulation: system design, electrical tests and in-vivo results
  77. An Embedded System Based on an IC for Neural Impedance Measurement
  78. A Custom dual-processor System for Real-time Neural Signal Processing
  79. A Telemonitoring Framework Designed for Elderly Patients
  80. Modelling and Automated Implementation of Optimal Power Saving Strategies in Coarse-Grained Reconfigurable Architectures
  81. Runtime Energy versus Quality Tuning in Motion Compensation Filters for HEVC
  82. Power modelling for saving strategies in coarse grained reconfigurable systems
  83. Reconfigurable coprocessors synthesis in the MPEG-RVC domain
  84. Computing Swarms for Self-Adaptiveness and Self-Organization in Floating-Point Array Processing
  85. Exploring custom heterogeneous MPSoCs for real-time neural signal decoding
  86. Automated Design Flow for Multi-Functional Dataflow-Based Platforms
  87. Automated power gating methodology for dataflow-based reconfigurable systems
  88. A configurable biopotentials acquisition module suitable for fetal electrocardiography studies
  89. Home telemonitoring of vital signs through a TV-based application for elderly patients
  90. Early Stage Automatic Strategy for Power-Aware Signal Processing Systems Design
  91. An HV-CMOS Integrated Circuit for Neural Stimulation in Prosthetic Applications
  92. Coarse-grained reconfiguration: dataflow-based power management
  93. Impact of Threshold Computation Methods in Hardware Wavelet Denoising Implementations for Neural Signal Processing
  94. Toward the Development of a Neuro-Controlled Bidirectional Hand Prosthesis
  95. A Temperature Transducer Based on a Low-Voltage Organic Thin-Film Transistor Detecting Pyroelectric Effect
  96. High performance, foldable, organic memories based on ultra-low voltage, thin film transistors
  97. The challenge of collaborative telerehabilitation: conception and evaluation of a telehealth system enhancement for home-therapy follow-up
  98. Tactile sensors with integrated piezoelectric polymer and low voltage organic thin-film transistors
  99. Power-awarness in coarse-grained reconfigurable designs: A dataflow based strategy
  100. An advanced algorithm for fetal heart rate estimation from non-invasive low electrode density recordings
  101. Real-time blind audio source separation: performance assessment on an advanced digital signal processor
  102. Automated design flow for coarse-grained reconfigurable platforms: An RVC-CAL multi-standard decoder use-case
  103. A Stream Buffer Mechanism for Pervasive Splitting Transformations on Polyhedral Process Networks
  104. Telemedicine Applied to Kinesiotherapy for Hand Dysfunction in Patients with Systemic Sclerosis and Rheumatoid Arthritis: Recovery of Movement and Telemonitoring Technology
  105. A Custom MPSoC Architecture With Integrated Power Management for Real-Time Neural Signal Decoding
  106. A Device for Local or Remote Monitoring of Hand Rehabilitation Sessions for Rheumatic Patients
  107. Behavioural models for analog to digital conversion architectures for deep submicron technology nodes
  108. ASAM: Automatic architecture synthesis and application mapping
  109. DSE and profiling of multi-context coarse-grained reconfigurable systems
  110. A system-level approach to adaptivity and fault-tolerance in NoC-based MPSoCs: The MADNESS project
  111. Exploring hardware support for scaling irregular applications on multi-node multi-core architectures
  112. THU0555 Validation of a Portable Device (RE.MO.TE.) for the Hand Functional Assessment in Patients with Chronic Rheumatic Diseases
  113. A collaborative approach to the telerehabilitation of patients with hand impairments
  114. An Integrated Portable Device for the Hand Functional Assessment in the Clinical Practice
  115. NInFEA: an embedded framework for the real-time evaluation of fetal ECG extraction algorithms
  116. The multi-dataflow composer tool: generation of on-the-fly reconfigurable platforms
  117. FPGA‐Based Emulation Support for Design Space Exploration
  118. ASAM: Automatic Architecture Synthesis and Application Mapping
  119. System Adaptivity and Fault-Tolerance in NoC-based MPSoCs: The MADNESS Project Approach
  120. Combining on-hardware prototyping and high-level simulation for DSE of multi-ASIP systems
  121. A sigma-delta architecture for recording of peripheral neural signals in prosthetic applications
  122. Concurrent hybrid switching for massively parallel systems-on-chip
  123. Multi-purpose systems: A novel dataflow-based generation and mapping strategy
  124. Enabling Fast ASIP Design Space Exploration: An FPGA-Based Runtime Reconfigurable Prototyper
  125. Exploiting binary translation for fast ASIP design space exploration on FPGAs
  126. A PORTABLE REAL-TIME MONITORING SYSTEM FOR KINESITHERAPIC HAND REHABILITATION EXERCISES
  127. The Multi-Dataflow Composer tool: A runtime reconfigurable HDL platform composer
  128. Cognitive screening in patients with amyotrophic lateral sclerosis in early stages
  129. Peripheral Neural Activity Recording and Stimulation System
  130. Towards self-adaptive networks on chip for massively parallel processors
  131. KeepInTouch: A telehealth system to improve the follow-up of chronic patients
  132. Real-time processing of tfLIFE neural signals on embedded DSP platforms: A case study
  133. RVC: A multi-decoder CAL Composer tool
  134. Enabling fast Network-on-Chip topology selection: an FPGA-based runtime reconfigurable prototyper
  135. Self organization on a swarm computing fabric
  136. An FPGA-Based Framework for Technology-Aware Prototyping of Multicore Embedded Architectures
  137. Exploiting FPGAs for technology-aware system-level evaluation of multi-core architectures
  138. A fast MPI-based parallel framework for cycle-accurate HDL multi-parametric simulations
  139. Impact of Half-Duplex and Full-Duplex DMA Implementations on NoC Performance
  140. Self-coordinated On-Chip Parallel Computing: A Swarm Intelligence Approach
  141. A DSP algorithm and system for real-time fetal ECG extraction
  142. A DVB-T framework for the remote monitoring of cardiopathic and diabetic patients
  143. A sleep apnoea keeper in a wearable device for Continuous detection and screening during daily life
  144. A Tele-home Care System Exploiting the DVB-T Technology and MHP
  145. A DVB-T BASED SYSTEM FOR THE DIFFUSION OF TELE-HOME CARE PRACTICE
  146. A Network on Chip Architecture for Heterogeneous Traffic Support with Non-Exclusive Dual-Mode Switching
  147. A pervasive telemedicine system exploiting the DVB-T technology
  148. On the impact of serialization on the cache performances in Network-on-Chip based MPSoCs
  149. Synthesis of Predictable Networks-on-Chip-Based Interconnect Architectures for Chip Multiprocessors
  150. Optimizing the serialization factor in Networks-on-Chip: a case of study
  151. Area and Power Modeling for Networks-on-Chip with Layout Awareness
  152. A Layout-Aware Analysis of Networks-on-Chip and Traditional Interconnects for MPSoCs
  153. Real-time foetal ECG extraction with JADE on floating point DSP
  154. Designing Application-Specific Networks on Chips with Floorplan Information
  155. Designing Message-Dependent Deadlock Free Networks on Chips for Application-Specific Systems on Chips
  156. Fully electronic DNA hybridization detection by a standard CMOS biochip
  157. Area and Power Modeling Methodologies for Networks-on-Chip
  158. Routing Aware Switch Hardware Customization for Networks on Chips
  159. Stigmergic approaches applied to flexible fault-tolerant digital VLSI architectures
  160. A CMOS, fully integrated sensor for electronic detection of DNA hybridization
  161. Reconfigurable Coprocessor for Multimedia Application Domain
  162. A charge-modulated FET for detection of biomolecular processes: conception, modeling, and simulation
  163. Automatic Application Partitioning on FPGA/CPU Systems Based on Detailed Low-Level Information
  164. Contrasting a NoC and a Traditional Interconnect Fabric with Layout Awareness
  165. Cooperative VLSI Tiled Architectures: Stigmergy in a Swarm Coprocessor
  166. A Low-Power Integrated Smart Sensor with on-Chip Real-Time Image Processing Capabilities
  167. Emergence of oscillations and spatio-temporal coherence states in a continuum-model of excitatory and inhibitory neurons
  168. A continuum-field model of visual cortex stimulus-driven behaviour: emergent oscillations and coherence fields
  169. A VLSI Multiplication-and-Add Scheme Based on Swarm Intelligence Approaches
  170. 44.6% processing cycles reduction in GSM voice coding by low-power reconfigurable co-processor architecture
  171. Analog computation for phase-based disparity estimation: continuous and discrete models
  172. Analogue VLSI primitives for perceptual tasks in machine vision
  173. Analysis and synthesis of double-layer MOSFET networks for smart sensory systems
  174. Design of an ASIP architecture for low-level visual elaborations
  175. Functional Periodic Intracortical Couplings Induced by Structured Lateral Inhibition in a Linear Cortical Network
  176. An analog VLSI computational engine for early vision tasks
  177. A VLSI Image Processing Architecture Dedicated to Real-Time Quality Control Analysis in an Industrial Plant
  178. A recurrent neural architecture mimicking cortical preattentive vision systems
  179. A programmable VLSI architecture based on multilayer CNN paradigms for real‐time visual processing
  180. Analysis and synthesis of resistive networks for distributed visual elaborations
  181. Adaptive resistive network for stereo depth estimation
  182. Resistive network implementing maps of Gabor functions of any phase
  183. A neuromorphic architecture for cortical multilayer integration of early visual tasks
  184. A Multi-Layer Analog VLSI Architecture for Texture Analysis Isomorphic to Cortical Cells in Mammalian Visual System
  185. Artificial visual orientation map implemented as an inhomogeneous active resistor mesh
  186. Anisotropic active resistor MESHES for implementing image processing operators
  187. A neural architectural model of simple and complex cortical cells
  188. A Novel Non-exclusive Dual-Mode Architecture for MPSoCs-Oriented Network on Chip Designs
  189. Designing Routing and Message-Dependent Deadlock Free Networks on Chips
  190. Run-time Adaptive Resources Allocation and Balancing on Nanoprocessors Arrays
  191. ×pipes Lite: A Synthesis Oriented Design Library For Networks on Chips
  192. A micro-power mixed signal IC for battery-operated burglar alarm systems
  193. A modular digital VLSI architecture for stereo depth estimation in industrial applications
  194. A distributed adaptive architecture for analog stereo depth estimation
  195. A neural network architectural model of visual cortical cells for texture segregation
  196. Neural clustering algorithms for classification and pre-placement of VLSI cells
  197. Pre-placement of VLSI blocks through learning neural networks