All Stories

  1. Accelerating the development of secure and reliable photonic and electronic systems
  2. Novel AI Accelerator Enabled by Integrated Photonics
  3. Silent Data Corruptions: Microarchitectural Perspectives
  4. Impact of Voltage Scaling on Soft Errors Susceptibility of Multicore Server CPUs
  5. Soft Error Effects on Arm Microprocessors: Early Estimations Versus Chip Measurements
  6. Anatomy of On-Chip Memory Hardware Fault Effects Across the Layers
  7. Soft Error Effects on Arm Microprocessors: Early Estimations versus Chip Measurements
  8. On the Evaluation of the Total-Cost-of-Ownership Trade-Offs in Edge vs Cloud Deployments: A Wireless-Denial-of-Service Case Study
  9. The Impact of CPU Voltage Margins on Power-Constrained Execution
  10. Demystifying the System Vulnerability Stack: Transient Fault Effects Across the Layers
  11. Exceeding Conservative Limits: A Consolidated Analysis on Modern Hardware Margins
  12. Demystifying Soft Error Assessment Strategies on Arm CPUs
  13. HealthLog Monitor: Errors, Symptoms and Reactions Consolidated
  14. Assessing the Effects of Low Voltage in Branch Prediction Units
  15. Adaptive Voltage/Frequency Scaling and Core Allocation for Balanced Energy and Performance on CPUs
  16. Analysis and Characterization of Ultra Low Power Branch Predictors
  17. Statistical Analysis of Multicore CPUs Operation in Scaled Voltage Conditions
  18. HealthLog Monitor: A Flexible System-Monitoring Linux Service
  19. Measuring and Exploiting Guardbands of Server-Grade ARMv8 CPU Cores and DRAMs
  20. Micro-Viruses for Fast System-Level Voltage Margins Characterization in Multicore CPUs
  21. An energy-efficient and error-resilient server ecosystem exceeding conservative scaling limits
  22. Harnessing voltage margins for energy efficiency in multicore CPUs
  23. Voltage margins identification on commercial x86-64 multicore microprocessors
  24. An Agile Post-Silicon Validation Methodology for the Address Translation Mechanisms of Modern Microprocessors
  25. Unveiling difficult bugs in address translation caching arrays for effective post-silicon validation
  26. ISA-independent post-silicon validation for the address translation mechanisms of modern microprocessors
  27. Microprocessor reliability-performance tradeoffs assessment at the microarchitecture level