All Stories

  1. Graph Neural Network based Initialization for Timing Driven Placement
  2. Variation-aware Analog Circuit Design via Contextual Modeling and Robust Optimization
  3. ChatArch: A Knowledge-driven Graph-of-thought LLM Framework for Processor Architecture Optimization
  4. ActiveEye: Enabling Continuous and Responsive Video Understanding for Smart Eyewear Systems
  5. Rethinking Logic Rewriting: Technology-Aware Subgraph Matching with Exact Synthesis
  6. GTN-Path: Efficient Path Timing Prediction through Waveform Propagation with Graph Transformer
  7. AcclMT: A Highly Resource-Efficient and Flexible Poseidon Hash-Based Merkle Tree Architecture
  8. Hierarchical Integration of Reinforcement Learning and Optimization Algorithms for Time-Efficient Design Automation of Complex Analog Circuit
  9. TL-CSE: Microarchitecture-Compiler Co-design Space Exploration via Transfer Learning
  10. Revisiting sensitivity-based analog sizing with derivative-aware Bayesian optimization and error-suppressed adjoint analysis
  11. FSMM: An Efficient Matrix Multiplication Accelerator Supporting Flexible Sparsity
  12. Physically Aware Synthesis Revisited: Guiding Technology Mapping with Primitive Logic Gate Placement
  13. AnalogGym: An Open and Practical Testing Suite for Analog Circuit Synthesis
  14. The Power of Graph Signal Processing for Chip Placement Acceleration
  15. PriorMSM: An Efficient Acceleration Architecture for Multi-Scalar Multiplication
  16. Gypsophila: A Scalable and Bandwidth-Optimized Multi-Scalar Multiplication Architecture
  17. Efficient ILT via Multigrid-Schwartz Method
  18. HiMOSS: A Novel High-dimensional Multi-objective Optimization Method via Adaptive Gradient-Based Subspace Sampling for Analog Circuit Sizing
  19. EVDMARL: Efficient Value Decomposition-based Multi-Agent Reinforcement Learning with Domain-Randomization for Complex Analog Circuit Design Migration
  20. Artisan: Automated Operational Amplifier Design via Domain-specific Large Language Model
  21. HMNTT: A Highly Efficient MDC-NTT Architecture for Privacy-preserving Applications
  22. Aries: A DNN Inference Scheduling Framework for Multi-core Accelerators
  23. Can Large Language Models Be Good Companions?
  24. FullSparse: A Sparse-Aware GEMM Accelerator with Online Sparsity Prediction
  25. D 3 PBO: D ynamic D omain D ecomposition based P arallel B aye...
  26. MACRO: Multi-agent Reinforcement Learning-based Cross-layer Optimization of Operational Amplifier
  27. Yield Optimization for Analog Circuits over Multiple Corners via Bayesian Neural Network: Enhancing Circuit Reliability under Environmental Variation
  28. CASES
  29. Graph Representation Learning for Microarchitecture Design Space Exploration
  30. TPNoC: An Efficient Topology Reconfigurable NoC Generator
  31. Guest Editor's Introduction: Machine Learning for VLSI Physical Design
  32. GraphPlanner: Floorplanning with Graph Neural Network
  33. Unveiling Causal Attention in Dogs' Eyes with Smart Eyewear
  34. ESPSim: An Efficient Scalable Power Grid Simulator Based on Parallel Algebraic Multigrid
  35. Efficient Layout Hotspot Detection via Neural Architecture Search
  36. LinEasyBO: Scalable Bayesian Optimization Approach for Analog Circuit Synthesis via One-Dimensional Subspaces
  37. Floorplanning with graph attention
  38. Do Smart Glasses Dream of Sentimental Visions?
  39. Automated Compensation Scheme Design for Operational Amplifier via Bayesian Optimization
  40. A Robust Batch Bayesian Optimization for Analog Circuit Synthesis via Local Penalization
  41. An Efficient Multi-fidelity Bayesian Optimization Approach for Analog Circuit Synthesis
  42. An efficient data reuse strategy for multi-pattern data access
  43. Efficient performance modeling via Dual-Prior Bayesian Model Fusion for analog and mixed-signal circuits
  44. Efficient performance modeling of analog integrated circuits via kernel density based sparse regression
  45. Subspace Trajectory Piecewise-Linear Model Order Reduction for Nonlinear Circuits
  46. Improved tangent space based distance metric for accurate lithographic hotspot classification