All Stories

  1. Reducing the Energy Consumption of sEMG-Based Gesture Recognition at the Edge Using Transformers and Dynamic Inference
  2. Efficient Deep Learning Models for Privacy-preserving People Counting on Low-resolution Infrared Arrays
  3. Automatic Layer Freezing for Communication Efficiency in Cross-Device Federated Learning
  4. Human Activity Recognition on Microcontrollers with Quantized and Adaptive Deep Neural Networks
  5. Monocular Depth Perception on Microcontrollers for Edge Applications
  6. Energy-Quality Scalable Monocular Depth Estimation on Low-Power CPUs
  7. Communication-Efficient Federated Learning with Gradual Layer Freezing
  8. Dynamic ConvNets on Tiny Devices via Nested Sparsity
  9. AxP: A HW-SW Co-Design Pipeline for Energy-Efficient Approximated ConvNets via Associative Matching
  10. ACME: An Energy-Efficient Approximate Bus Encoding for I2C
  11. Ultra-compact binary neural networks for human activity recognition on RISC-V processors
  12. TVFS: Topology Voltage Frequency Scaling for Reliable Embedded ConvNets
  13. Manufacturing as a Data-Driven Practice: Methodologies, Technologies, and Tools
  14. EAST: Encoding-Aware Sparse Training for Deep Memory Compression of ConvNets
  15. TentacleNet: A Pseudo-Ensemble Template for Accurate Binary Convolutional Neural Networks
  16. Efficacy of Topology Scaling for Temperature and Latency Constrained Embedded ConvNets
  17. Logic Synthesis of Pass-Gate Logic Circuits With Emerging Ambipolar Technologies
  18. Corrigendum to“Approximate error detection-correction for efficient adaptive voltage Over-Scaling”[Integration 63 (2018) 220–231]
  19. Fast and Accurate Inference on Microcontrollers With Boosted Cooperative Convolutional Neural Networks (BC-Net)
  20. Performance Profiling of Embedded ConvNets under Thermal-Aware DVFS
  21. CoopNet: Cooperative Convolutional Neural Network for Low-Power MCUs
  22. Integer ConvNets on Embedded CPUs: Tools and Performance Assessment on the Cortex-A Cores
  23. Arbitrary-Precision Convolutional Neural Networks on Low-Power IoT Processors
  24. Inference on the Edge: Performance Analysis of an Image Classification Task Using Off-The-Shelf CPUs and Open-Source ConvNets
  25. Implementing Adaptive Voltage Over-Scaling: Algorithmic Noise Tolerance vs. Approximate Error Detection
  26. Enabling Energy-Efficient Unsupervised Monocular Depth Estimation on ARMv7-Based Platforms
  27. Energy-Efficient Convolutional Neural Networks via Recurrent Data Reuse
  28. SAID: A Supergate-Aided Logic Synthesis Flow for Memristive Crossbars
  29. Optimality Assessment of Memory-Bounded ConvNets Deployed on Resource-Constrained RISC Cores
  30. Energy-Accuracy Scalable Deep Convolutional Neural Networks: A Pareto Analysis
  31. On the Efficiency of Early Bird Sampling (EBS) an Error Detection-Correction Scheme for Data-Driven Voltage Over-Scaling
  32. Layer-Wise Compressive Training for Convolutional Neural Networks
  33. Logic-In-Memory Architecture For Min/Max Search
  34. Energy-Driven Precision Scaling for Fixed-Point ConvNets
  35. Inferential Logic: a Machine Learning Inspired Paradigm for Combinational Circuits
  36. Approximate Error Detection-Correction for efficient Adaptive Voltage Over-Scaling
  37. Quasi-exact logic functions through classification trees
  38. Weak-MAC: Arithmetic Relaxation for Dynamic Energy-Accuracy Scaling in ConvNets
  39. Design-Space Exploration of Pareto-Optimal Architectures for Deep Learning with DVFS
  40. Multiplication by Inference using Classification Trees: A Case-Study Analysis
  41. All-digital embedded meters for on-line power estimation
  42. Energy-performance design exploration of a low-power microprogrammed deep-learning accelerator
  43. Adaptive Convolutional Neural Networks
  44. A compression-driven training framework for embedded deep neural networks
  45. Early bird sampling: A short-paths free error detection-correction strategy for data-driven VOS
  46. Activation-Kernel Extraction through Machine Learning
  47. Tunable Error Detection-Correction for Efficient Adaptive Voltage Over-Scaling
  48. Beyond Ideal DVFS Through Ultra-Fine Grain Vdd-Hopping
  49. Logic Synthesis for Silicon and Beyond-Silicon Multi-gate Pass-Logic Circuits
  50. Quasi-Adiabatic Logic Arrays for Silicon and Beyond-Silicon Energy-Efficient ICs
  51. Ultra-Fine Grain Vdd-Hopping for energy-efficient Multi-Processor SoCs
  52. Multi-function logic synthesis of silicon and beyond-silicon ultra-low power pass-gates circuits
  53. Enabling quasi-adiabatic logic arrays for silicon and beyond-silicon technologies
  54. Graphene-PLA (GPLA)
  55. Ultra-low power circuits using graphene p–n junctions and adiabatic computing
  56. An automated design flow for approximate circuits based on reduced precision redundancy
  57. One-pass logic synthesis for graphene-based Pass-XNOR logic circuits
  58. Characterizing the Activity Factor in NBTI Aging Models for Embedded Cores
  59. Design and Characterization of Analog-to-Digital Converters using Graphene P-N Junctions
  60. Exploiting the Expressive Power of Graphene Reconfigurable Gates via Post-Synthesis Optimization
  61. Evaluating a Hardware-Based Approach for Detecting Resistive-Open Defects in SRAMs
  62. Power-Gating for Leakage Control and Beyond
  63. Ultra Low-Power Computation via Graphene-Based Adiabatic Logic Gates
  64. Modeling of Physical Defects in PN Junction Based Graphene Devices
  65. Row-based body-bias assignment for dynamic thermal clock-skew compensation
  66. Dynamic Indexing: Leakage-Aging Co-Optimization for Caches
  67. Pass-XNOR logic: A new logic style for P-N junction based graphene circuits
  68. Modeling and characterization of thermally induced skew on clock distribution networks of nanometric ICs
  69. Power modeling and characterization of Graphene-based logic gates
  70. Exploration of different implementation styles for graphene-based reconfigurable gates
  71. Investigating the behavior of physical defects in pn-junction based reconfigurable graphene devices
  72. Technique based on On-Chip Current Sensors and Neighbourhood Comparison Logic to detect resistive-open defects in SRAMs
  73. Layout-Driven Post-Placement Techniques for Temperature Reduction and Thermal Gradient Minimization
  74. Delay model for reconfigurable logic gates based on graphene PN-junctions
  75. Energy-optimal SRAM supply voltage scheduling under lifetime and error constraints
  76. On-Chip NBTI and PBTI Tracking through an All-Digital Aging Monitor Architecture
  77. Design Techniques and Architectures for Low-Leakage SRAMs
  78. Design Techniques for NBTI-Tolerant Power-Gating Architectures
  79. NBTI-Aware Data Allocation Strategies for Scratchpad Based Embedded Systems
  80. Energy-optimal caches with guaranteed lifetime
  81. NBTI effects on tree-like clock distribution networks
  82. On-chip process variation-tracking through an all-digital monitoring architecture
  83. Power Efficient Variability Compensation Through Clustered Tunable Power-Gating
  84. A new Built-In Current Sensor scheme to detect dynamic faults in Nano-Scale SRAMs
  85. NBTI-aware data allocation strategies for scratchpad memory based embedded systems
  86. An On-Chip All-Digital PV-Monitoring Architecture for Digital IPs
  87. Buffering of frequent accesses for reduced cache aging
  88. Sub-Row Sleep Transistor Insertion for Concurrent Clock-Gating and Power-Gating
  89. NBTI-Aware Clustered Power Gating
  90. Temperature-Insensitive Dual-$V_{\rm th}$ Synthesis for Nanometer CMOS Technologies Under Inverse Temperature Dependence
  91. Dual- assignment policies in ITD-aware synthesis
  92. Analysis of NBTI-induced SNM degradation in power-gated SRAM cells
  93. Aging effects of leakage optimizations for caches
  94. An integrated thermal estimation framework for industrial embedded platforms
  95. Dynamic indexing
  96. Generating power-hungry test programs for power-aware validation of pipelined processors
  97. On-chip Thermal Modeling Based on SPICE Simulation
  98. Reducing Timing Overhead in Simultaneously Clock-Gated and Power-Gated Designs by Placement-Aware Clustering
  99. Design of a Flexible Reactivation Cell for Safe Power-Mode Transition in Power-Gated Circuits
  100. Placement-aware clustering for integrated clock and power gating
  101. NBTI-aware power gating for concurrent leakage and aging optimization
  102. NBTI-aware sleep transistor design for reliable power-gating
  103. Thermal-Aware Design Techniques for Nanometer CMOS Circuits
  104. Ensuring temperature-insensitivity of dual-Vt designs through ITD-aware synthesis
  105. On quantifying the figures of merit of power-gating for leakage power minimization in nanometer CMOS circuits
  106. Optimal MTCMOS Reactivation Under Power Supply Noise and Performance Constraints
  107. Integrating Clock Gating and Power Gating for Combined Dynamic and Leakage Power Optimization in Digital CMOS Circuits
  108. Reducing leakage power by accounting for temperature inversion dependence in dual-Vt synthesized circuits
  109. Temperature-insensitive synthesis using multi-vt libraries
  110. Efficient Computation of Discharge Current Upper Bounds for Clustered Sleep Transistor Sizing
  111. Design of a family of sleep transistor cells for a clustered power-gating flow in 65nm technology