All Stories

  1. A flexible task graph for any C application
  2. A Study on Hyperparameters Configurations for an Efficient Human Activity Recognition System
  3. A methodology and framework for software memoization of functions
  4. Improving Performance and Energy Consumption in Embedded Systems via Binary Acceleration: A Survey
  5. Compiler Techniques for Efficient MATLAB to OpenCL Code Generation
  6. Introduction to the Special Section on FPL 2015
  7. The First 25 Years of the FPL Conference
  8. Foreword to the special issue of the 18th IEEE international conference on computational science and engineering (CSE2015)
  9. SSA-based MATLAB-to-C compilation and optimization
  10. The ANTAREX approach to autotuning and adaptivity for energy efficient HPC systems
  11. A MATLAB subset to C compiler targeting embedded systems
  12. Clustering-Based Selection for the Exploration of Compiler Optimization Sequences
  13. Guest Editorial ARC 2014
  14. Techniques for efficient MATLAB-to-C compilation
  15. Guest Editorial FPL 2013
  16. C and OpenCL generation from MATLAB
  17. Transparent Acceleration of Program Execution using Reconfigurable Hardware
  18. Performance-driven instrumentation and mapping strategies using the LARA aspect-oriented programming approach
  19. Enabling FPGA routing configuration sharing in dynamic partial reconfiguration
  20. Trace-Based Reconfigurable Acceleration with Data Cache and External Memory Support
  21. A clustering-based approach for exploring sequences of compiler optimizations
  22. Exploration of compiler optimization sequences using clustering-based selection
  23. High-Level Synthesis from C vs. a DSL-Based Approach
  24. Reconfigurable Computing: Architectures, Tools, and Applications
  25. Multi-Target C Code Generation from MATLAB
  26. Coarse/Fine-grained Approaches for Pipelining Computing Stages in FPGA-Based Multicore Architectures
  27. Exploration of compiler optimization sequences using clustering-based selection
  28. General chair message
  29. Transparent Trace-Based Binary Acceleration for Reconfigurable HW/SW Systems
  30. Enriching MATLAB with aspect-oriented features for developing embedded systems
  31. The MATISSE MATLAB compiler
  32. Related Work
  33. Introduction
  34. Compilation and Synthesis for Embedded Reconfigurable Systems
  35. The LARA Language
  36. Conclusions
  37. Architecture for Transparent Binary Acceleration of Loops with Memory Accesses
  38. Transparent Runtime Migration of Loop-Based Traces of Processor Instructions to Reconfigurable Processing Units
  39. LARA Experiments
  40. An Automatic Tool Flow for the Combined Implementation of Multi-mode Circuits
  41. An FPGA-based multi-core approach for pipelining computing stages
  42. The REFLECT Design-Flow
  43. Resource-Efficient Designs Using an Aspect-Oriented Approach
  44. Controlling Hardware Synthesis with Aspects
  45. Hardware pipelining of runtime-detected loops
  46. Programming strategies for runtime adaptability
  47. Hardware/software specialization through aspects: The LARA approach
  48. Analysis of error detection schemes: Toolchain support and hardware/software implications
  49. Specifying Compiler Strategies for FPGA-based Systems
  50. LARA
  51. Program and Aspect Metrics for MATLAB
  52. Experiments with the LARA aspect-oriented approach
  53. From Instruction Traces to Specialized Reconfigurable Arrays
  54. Techniques for Dynamically Mapping Computations to Coprocessors
  55. Identifying Merge-Beneficial Software Kernels for Hardware Implementation
  56. LALP: A Language to Program Custom FPGA-Based Acceleration Engines
  57. A Domain-Specific Language for the Specification of Adaptable Context Inference
  58. Fast placement and routing by extending coarse-grained reconfigurable arrays with Omega Networks
  59. Programming safety requirements in the REFLECT design flow
  60. Reconfigurable Computing
  61. Conclusion
  62. Introduction
  63. Selected Papers from the 17th Reconfigurable Architectures Workshop (RAW2010)
  64. Code Transformations for Embedded Reconfigurable Computing Architectures
  65. REFLECT: Rendering FPGAs to Multi-core Embedded Computing
  66. On identifying and optimizing instruction sequences for dynamic compilation
  67. A Query Processing Strategy for Conceptual Queries Based on Object-Role Modeling
  68. On Identifying Segments of Traces for Dynamic Compilation
  69. On Identifying Patterns in Code Repositories to Assist the Generation of Hardware Templates
  70. On using LALP to map an audio encoder/decoder on FPGAs
  71. Compiling for reconfigurable computing
  72. Providing user context for mobile and social networking applications
  73. Welcome message
  74. Preprocessing techniques for context recognition from accelerometer data
  75. Unbalanced FIFO sorting for FPGA-based systems
  76. A comparison of three representative hardware sorting units
  77. LALP: A Novel Language to Program Custom FPGA-Based Architectures
  78. Automatic generation of FPGA hardware accelerators using a domain specific language
  79. Compilation Techniques for Reconfigurable Architectures
  80. The current feasibility of gesture recognition for a smartphone using J2ME
  81. An Analysis of Navigation Algorithms for Smartphones Using J2ME
  82. Mobile Context Provider for Social Networking
  83. Synthesis of regular expressions for FPGAs
  84. IJE special issue on reconfigurable hardware systems
  85. Retargeting, Evaluating, and Generating Reconfigurable Array-Based Architectures
  86. Combining Rewriting-Logic, Architecture Generation, and Simulation to Exploit Coarse-Grained Reconfigurable Architectures
  87. Introduction
  88. Compilers for Reconfigurable Architectures
  89. Overview of Reconfigurable Architectures
  90. Final Remarks
  91. Code Transformations
  92. Compilation and Synthesis Flows
  93. Mapping and Execution Optimizations
  94. Perspectives on Programming Reconfigurable Computing Platforms
  95. Regular Expression Matching in Reconfigurable Hardware
  96. Aggressive Loop Pipelining for Reconfigurable Architectures
  97. An FPGA Implementation for a Kalman Filter with Application to Mobile Robotics
  98. On Adapting Power Estimation Models for Embedded Soft-Core Processors
  99. A Data-Driven Approach for Pipelining Sequences of Data-Dependent Loops
  100. Reconfigurable Computing: Architectures, Tools and Applications
  101. A Polynomial Placement Algorithm for Data Driven Coarse-Grained Reconfigurable Architectures
  102. Using Rewriting Logic to Match Patterns of Instructions from a Compiler Intermediate Form to Coarse-Grained Processing Elements
  103. A Methodology to Design FPGA-based PID Controllers
  104. Mesh Mapping Exploration for Coarse-Grained Reconfigurable Array Architectures
  105. Reconfigurable Computing: Architectures and Applications
  106. New challenges in computer science education
  107. Dynamic loop pipelining in data-driven architectures
  108. New challenges in computer science education
  109. Data-Driven Regular Reconfigurable Arrays: Design Space Exploration and Mapping
  110. Self-loop Pipelining and Reconfigurable Dataflow Arrays
  111. Modeling Loop Unrolling: Approaches and Open Issues
  112. An Environment for Exploring Data-Driven Architectures
  113. XPP-VC: A C Compiler with Temporal Partitioning for the PACT-XPP Architecture
  114. Compilation Increasing the Scheduling Scope for Multi-memory-FPGA-Based Custom Computing Machines
  115. An Enhanced Static-List Scheduling Algorithm for Temporal Partitioning onto RPUs
  116. Architectures and compilers to support reconfigurable computing
  117. Compilation and Temporal Partitioning for a Coarse-grain Reconfigurable Architecture
  118. Synthesis of Regular Expressions Targeting FPGAs: Current Status and Open Issues
  119. The Role of Programming Models on Reconfigurable Computing Fabrics