All Stories

  1. A flexible task graph for any C application
  2. A CPU-FPGA Holistic Source-To-Source Compilation Approach for Partitioning and Optimizing C/C++ Applications
  3. A Study on Hyperparameters Configurations for an Efficient Human Activity Recognition System
  4. A methodology and framework for software memoization of functions
  5. Improving Performance and Energy Consumption in Embedded Systems via Binary Acceleration: A Survey
  6. Compiler Techniques for Efficient MATLAB to OpenCL Code Generation
  7. Introduction to the Special Section on FPL 2015
  8. The First 25 Years of the FPL Conference
  9. Foreword to the special issue of the 18th IEEE international conference on computational science and engineering (CSE2015)
  10. SSA-based MATLAB-to-C compilation and optimization
  11. The ANTAREX approach to autotuning and adaptivity for energy efficient HPC systems
  12. A MATLAB subset to C compiler targeting embedded systems
  13. Clustering-Based Selection for the Exploration of Compiler Optimization Sequences
  14. Guest Editorial ARC 2014
  15. Techniques for efficient MATLAB-to-C compilation
  16. Guest Editorial FPL 2013
  17. C and OpenCL generation from MATLAB
  18. Transparent Acceleration of Program Execution using Reconfigurable Hardware
  19. Performance-driven instrumentation and mapping strategies using the LARA aspect-oriented programming approach
  20. Enabling FPGA routing configuration sharing in dynamic partial reconfiguration
  21. Trace-Based Reconfigurable Acceleration with Data Cache and External Memory Support
  22. A clustering-based approach for exploring sequences of compiler optimizations
  23. Exploration of compiler optimization sequences using clustering-based selection
  24. High-Level Synthesis from C vs. a DSL-Based Approach
  25. Reconfigurable Computing: Architectures, Tools, and Applications
  26. Multi-Target C Code Generation from MATLAB
  27. Coarse/Fine-grained Approaches for Pipelining Computing Stages in FPGA-Based Multicore Architectures
  28. Exploration of compiler optimization sequences using clustering-based selection
  29. General chair message
  30. Transparent Trace-Based Binary Acceleration for Reconfigurable HW/SW Systems
  31. Enriching MATLAB with aspect-oriented features for developing embedded systems
  32. The MATISSE MATLAB compiler
  33. Related Work
  34. Introduction
  35. Compilation and Synthesis for Embedded Reconfigurable Systems
  36. The LARA Language
  37. Conclusions
  38. Architecture for Transparent Binary Acceleration of Loops with Memory Accesses
  39. Transparent Runtime Migration of Loop-Based Traces of Processor Instructions to Reconfigurable Processing Units
  40. LARA Experiments
  41. An Automatic Tool Flow for the Combined Implementation of Multi-mode Circuits
  42. An FPGA-based multi-core approach for pipelining computing stages
  43. The REFLECT Design-Flow
  44. Resource-Efficient Designs Using an Aspect-Oriented Approach
  45. Controlling Hardware Synthesis with Aspects
  46. Hardware pipelining of runtime-detected loops
  47. Programming strategies for runtime adaptability
  48. Hardware/software specialization through aspects: The LARA approach
  49. Analysis of error detection schemes: Toolchain support and hardware/software implications
  50. Specifying Compiler Strategies for FPGA-based Systems
  51. LARA
  52. Program and Aspect Metrics for MATLAB
  53. Experiments with the LARA aspect-oriented approach
  54. From Instruction Traces to Specialized Reconfigurable Arrays
  55. Techniques for Dynamically Mapping Computations to Coprocessors
  56. Identifying Merge-Beneficial Software Kernels for Hardware Implementation
  57. LALP: A Language to Program Custom FPGA-Based Acceleration Engines
  58. A Domain-Specific Language for the Specification of Adaptable Context Inference
  59. Fast placement and routing by extending coarse-grained reconfigurable arrays with Omega Networks
  60. Programming safety requirements in the REFLECT design flow
  61. Reconfigurable Computing
  62. Conclusion
  63. Introduction
  64. Selected Papers from the 17th Reconfigurable Architectures Workshop (RAW2010)
  65. Code Transformations for Embedded Reconfigurable Computing Architectures
  66. REFLECT: Rendering FPGAs to Multi-core Embedded Computing
  67. On identifying and optimizing instruction sequences for dynamic compilation
  68. A Query Processing Strategy for Conceptual Queries Based on Object-Role Modeling
  69. On Identifying Segments of Traces for Dynamic Compilation
  70. On Identifying Patterns in Code Repositories to Assist the Generation of Hardware Templates
  71. On using LALP to map an audio encoder/decoder on FPGAs
  72. Compiling for reconfigurable computing
  73. Providing user context for mobile and social networking applications
  74. Welcome message
  75. Preprocessing techniques for context recognition from accelerometer data
  76. Unbalanced FIFO sorting for FPGA-based systems
  77. A comparison of three representative hardware sorting units
  78. LALP: A Novel Language to Program Custom FPGA-Based Architectures
  79. Automatic generation of FPGA hardware accelerators using a domain specific language
  80. Compilation Techniques for Reconfigurable Architectures
  81. The current feasibility of gesture recognition for a smartphone using J2ME
  82. An Analysis of Navigation Algorithms for Smartphones Using J2ME
  83. Mobile Context Provider for Social Networking
  84. Synthesis of regular expressions for FPGAs
  85. IJE special issue on reconfigurable hardware systems
  86. Retargeting, Evaluating, and Generating Reconfigurable Array-Based Architectures
  87. Combining Rewriting-Logic, Architecture Generation, and Simulation to Exploit Coarse-Grained Reconfigurable Architectures
  88. Introduction
  89. Compilers for Reconfigurable Architectures
  90. Overview of Reconfigurable Architectures
  91. Final Remarks
  92. Code Transformations
  93. Compilation and Synthesis Flows
  94. Mapping and Execution Optimizations
  95. Perspectives on Programming Reconfigurable Computing Platforms
  96. Regular Expression Matching in Reconfigurable Hardware
  97. Aggressive Loop Pipelining for Reconfigurable Architectures
  98. An FPGA Implementation for a Kalman Filter with Application to Mobile Robotics
  99. On Adapting Power Estimation Models for Embedded Soft-Core Processors
  100. A Data-Driven Approach for Pipelining Sequences of Data-Dependent Loops
  101. Reconfigurable Computing: Architectures, Tools and Applications
  102. A Polynomial Placement Algorithm for Data Driven Coarse-Grained Reconfigurable Architectures
  103. Using Rewriting Logic to Match Patterns of Instructions from a Compiler Intermediate Form to Coarse-Grained Processing Elements
  104. A Methodology to Design FPGA-based PID Controllers
  105. Mesh Mapping Exploration for Coarse-Grained Reconfigurable Array Architectures
  106. Reconfigurable Computing: Architectures and Applications
  107. New challenges in computer science education
  108. Dynamic loop pipelining in data-driven architectures
  109. New challenges in computer science education
  110. Data-Driven Regular Reconfigurable Arrays: Design Space Exploration and Mapping
  111. Self-loop Pipelining and Reconfigurable Dataflow Arrays
  112. Modeling Loop Unrolling: Approaches and Open Issues
  113. An Environment for Exploring Data-Driven Architectures
  114. XPP-VC: A C Compiler with Temporal Partitioning for the PACT-XPP Architecture
  115. Compilation Increasing the Scheduling Scope for Multi-memory-FPGA-Based Custom Computing Machines
  116. An Enhanced Static-List Scheduling Algorithm for Temporal Partitioning onto RPUs
  117. Architectures and compilers to support reconfigurable computing
  118. Compilation and Temporal Partitioning for a Coarse-grain Reconfigurable Architecture
  119. Synthesis of Regular Expressions Targeting FPGAs: Current Status and Open Issues
  120. The Role of Programming Models on Reconfigurable Computing Fabrics